Classes | |
class | tcDspAd56x5 |
Instances of this class handle access to a Analog Devices Ad56x5 digital-to-analog converter via the generic I2c interface for the MityDSP. More... | |
class | tcDspAdc1278 |
Instances of this class create an interface to an ADS1278 24-bit analog to digital converter. More... | |
class | tcDspAdc776X |
Instances of this class create an interface to an ADC776X 24-bit sigma delta analog to digital converter. More... | |
class | tcDspAdc776XBaseConfig |
< Masks used to enable channels for round-robin capture More... | |
class | tcDspAdc776XBase |
class | tcDspAdc7844 |
Instances of this class create an interface to an ADS7844 12-bit analog to digital converter. More... | |
class | tcDspAdc8329 |
Instances of this class create an interface to an ADS8329 16-bit analog to digital converter. More... | |
class | tcDspAdc8343 |
Instances of this class handle access to the ADS8343 or ADS8344 analog-to-digital converters, using the high speed ADC MityDSP core. More... | |
class | tcDspAdc834xMcBsp |
Instances of this class create an interface to an ADS834x 16-bit analog to digital converter. More... | |
class | tcDspAdc8402 |
Instances of this class create an interface to an ADS8402 16-bit analog to digital converter. More... | |
class | tcDspAdc9235 |
Instances of this class create an interface to an ADC9235 12-bit analog to digital converter. More... | |
class | tcDspAdcBaseConfig |
The tcDspAdcBaseConfig class provides a simple configuration structure that may be used when initializing a tcDspAdcBase derived interface class. More... | |
class | tcDspAdcBase |
Instances of this class handle. More... | |
class | tcDspAta |
The tcDspAta class is used for low-level reading and writing to ATA storage devices such as disk drives or CompactFlash cards. More... | |
class | tcDspAutoLCK |
A utility class to manage the automatic release of LCK's. More... | |
class | tcDspAwg |
Instances of this class handle configuring, and enabling the MityDSP Arbitrary Waveform Generator core I/O interface. More... | |
class | tcDspAwgDual |
Instances of this class handle configuring, and enabling the MityDSP Dual Arbitrary Waveform Generator core I/O interface. More... | |
class | tcDspBankSelect |
The tcDspBankSelect class is used to change the currently selected Flash bank. More... | |
class | tcDspBootstrapper |
Static class to provide access to the MityDSP CLUB Bootstrapper to load a new executable. More... | |
class | tcDspBootloader |
Static class to provide application level wrappers for reprogramming MityDSP application and bootloader FPGA and DSP images from a running application. More... | |
class | tcDspBufPool |
The tcDspBufPool class is a singleton that manages a set of standard buffer pools ranging in size from 16 bytes to 64K bytes. More... | |
class | tcDspCameraLink |
Instances of this class handle. More... | |
class | tcDspCircBuffer |
The tcDspCircBuffer class provides a thread safe circular buffer interface supporting arbitrary size and arbitrary read/write requests. More... | |
class | tcDspCircularIndex |
The tcDspCircularIndex class maintains a circular index and manages the read and write pointers. More... | |
class | tcDspClk1305G |
Instances of this class handle an interface to the frequency-adjustable HW clock core, based upon Appendix G of RFC-1305 (NTP). More... | |
class | tcDspConfig |
This is a singleton class. More... | |
class | tcDspCounter |
The tcDspCounter class is used to interface to the MityDSP event counter core. More... | |
class | tcDspCs552x |
The tcDspCs552x class is used to set up and receive data from a Crystal CS552X family A-to-D converter. More... | |
class | tcDspDac7616 |
Class used to provide interfacing to a BurrBrown DAC7616 Quad digital to analog converter circuit. More... | |
class | tcDspDac8532McBsp |
Instances of this class create an interface to an ADS834x 16-bit analog to digital converter. More... | |
class | tcDspDac8534 |
Instances of this class handle access to a TI DAC8534 digital-to-analog converter via the generic SPI interface for the MityDSP. More... | |
class | tcDspDacAd420 |
Instances of this class handle access to an Analog Devices AD420 digital-to-current loop converter via the generic SPI interface for the MityDSP. More... | |
class | tcDspDacBaseMcBsp |
Base class for digital-to-analog converter devices using the MityDSP McBSP interface. More... | |
class | tcDspDacTlv5610 |
Class used to provide interfacing to a TI TLV5610 8-channel digital- to-analog converter via the MityDSP McBSP. More... | |
class | tcDspDisplay |
The tcDspDisplay class allows the user to draw, erase, write text and bitmaps on a simple memory mapped display interface. More... | |
class | tcDspDisplayDriver |
The tcDspDisplayDriver class is a base class to provide generic access to a display frame buffer via the tcDspFpgaDma class. More... | |
class | tcDspError |
The tcDspError class handles formatting and reporting errors in a consistent manner. More... | |
union | tuFirmwareVersion |
union | tuInterruptInfo |
union | tuBootstrapVerInfo |
union | tuBootstrapDateInfo |
class | tcDspFirmware |
Static class to provide access to core-independent features of the MityDSP firmware. More... | |
class | tcDspFlash |
The tcDspFlash class may be used to write to and read from a Flash memory device. More... | |
class | tcDspFont |
The tcDspFont class allows various fixed and proportional fonts to be defined for use (with tcDspDisplay, for example). More... | |
class | tcDspFpgaDma |
The tcDspFpgaDma class provides the MityDSP FPGA with DMA access to blocks of DSP memory. More... | |
class | tcDspFpgaIir |
Instances of this class handle configuring and setting up the coefficients for the IIR Filter core. More... | |
class | tcDspFtdiVNC1 |
class | tcDspFtdiUsbFs |
class | tcDspGpio |
Instances of this class handle sending, receiving, and configuring a register containing 32 general purpose I/O pins. More... | |
class | tcDspHsUsb |
Instances of this class handle an interface to the high-speed USB device This device is theoretically capable of speeds up to 400 Mbps. More... | |
class | tcDspI2c |
Instances of this class handle access to a "generic" implementation of the I2C interface for the MityDSP. More... | |
class | tcDspI2c2 |
Instances of this class handle access to a "generic" implementation of the I2C interface, version 2.0, for the MityDSP. More... | |
class | tcDspInterruptDispatch |
Static class to provide interrupt dispatching capabilities for the external interrupt pins (levels 4-7) of the MityDSP. More... | |
class | tcDspLcd |
The tcDspLcd class provides general access to an LCD 5-6-5 Display device. More... | |
class | tcDspLvds |
Instances of this class handle access to a "generic" implementation of the LVDS interface for the MityDSP. More... | |
class | tcDspMcbspConfig |
The tcDspMcbspConfig class provides a simple initialization structure for purposes of configuring a tcDspMcbsp class instance. More... | |
class | tcDspMcbsp |
The tcDspMcbsp class is used for communications via the Texas Instruments Multichannel Buffered Serial Port (McBSP). More... | |
class | tcDspMmc |
Instances of this class handle access to a MultiMedia Card via the MityDSP SPI interface. More... | |
class | tcDspOutputLatch |
Class used to create an output latch interface (for use as a chip selector or other control line). More... | |
class | tcDspParserBase |
This class provides a base class from which various MityDSP parsers may be derived. More... | |
class | tcDspParseIHex |
Instances of this class may be used to parse an Intel HEX file into an application-provided buffer. More... | |
class | tcDspPulseIntegrator |
The tcDspPulseIntegrator class is used to interface to the MityDSP pulse integrator core. More... | |
class | tcDspPwmConfig |
The tcDspPwmConfig class provides a simple initialization structure for the purposes of configuring a tcDspPwm core class instance. More... | |
class | tcDspPwm |
Instances of this class handle configuring, and enabling the MityDSP Pulse Width Modulator core I/O interface. More... | |
class | tcDspQDMA |
Instances of this class handle sending, receiving, and configuring Quick DMA tranfers. More... | |
class | tcDspQvga16 |
The tcDspQvga16 class provides access to a 16-bit color QVGA (320x240 pixel) display device. More... | |
class | tcDspRamBlock |
The tcDspRamBlock class is a virtual base class to provide consistent access to various firmware cores that adhere to the RAM Block interface. More... | |
struct | tsDspRomFsNode |
This structure is used to define a ROM filesystem node. More... | |
class | tcDspRomFs |
struct | tsCLTime |
class | tcDspRtcBase |
The tcDspRtcBase class is a virtual base class to provide consistent access to various real-time clock devices. More... | |
class | tcDspRtcDS1305 |
Instances of this class handle access to the DS1305 real-time clock chip. More... | |
class | tcDspRtcM41T81 |
Instances of this class handle access to the M41T81 real-time clock chip. More... | |
class | tcDspSerial |
Instances of this class handle sending, receiving, and configuring a serial port. More... | |
class | tcDspSpi |
Instances of this class handle access to a "generic" implementation of the SPI interface for the MityDSP. More... | |
class | tcDspStepperConfig |
The tcDspStepperConfig class provides a simple initialization structure for the purposes of configuring a tcDspStepper core class instance. More... | |
class | tcDspStepper |
Instances of this class handle configuring, and enabling the MityDSP base Stepper Motor Controller core I/O interface. More... | |
class | tcDspStorageBase |
The tcDspStorageBase class is a base class to define a consistent set of interfaces for all storage devices. More... | |
class | tcDspStorageCache |
Instances of this class provide a simple cache between an application or filesystem (or other) driver. More... | |
class | tcDspStorageProxy |
The tcDspStorageProxy class is used with other tcDspStorageBase derived classes to provide an interface that presents a given sector size. More... | |
class | tcDspThermBase |
The tcDspThermBase class is a virtual base class to provide consistent access to various thermistor devices. More... | |
class | tcDspThermERTJV1G |
Instances of this class handle storing and computing values for a Panasonic ERTJV1G thermistor. More... | |
class | tcDspTimer |
This class is the MityDSP timer object. More... | |
class | tcDspTimingGenerator |
The tcDspTimingGenerator class is used to interface to the MityDSP Timing Generator core. More... | |
union | tuCfrReg |
class | tcDspTlv254x |
The tcDspTlv254x class is used to set up and receive data from a TI TLV254X family A-to-D converter. More... | |
class | tcDspTmp0506 |
Instances of this class handle access to the TMP05/06 temperature sensors. More... | |
class | tcDspTouchScreen |
The tcDspTouchScreen class provides access to a 4-wire touch screen overlay device. More... | |
class | tcDspWatchdog |
Static class to provide the ability to enable and manage the watchdog timer core of the MityDSP. More... |
Typedefs | |
typedef class tcDspAdc8343 | tcDspAdc8344 |
< Also supports the ADS8344, so allow these names, too | |
typedef class tcDspAdc8343 | tcDspAdc834x |
typedef void(* | tfErrorCallback )(enum teErrorValues, const char *) |
Prototypes for the tcDspError callbacks. | |
typedef void(* | tfLogCallback )(const char *, int, teErrorValues) |
typedef void(* | tfMediaCallback )(bool, void *) |
typedef int(* | tfIsrCallback )(Arg) |
Prototype for the tcDspInterruptDispatch ISR callback. |
Enumerations | |
enum | teFIFOLevel { eeEmpty, eeOneQ, eeHalf, eeThreeQ, eeFull } |
The teFIFOLevel enumeration defines the various FIFO levels that may be checked for the tcDspAdcBase class. More... | |
enum | teErrorValues { debug = 0, status = 1, warning = 2, error = 3, none = 4 } |
This enumeration lists the available message severities. More... | |
enum | teTimeFormats { eeHHMMSS, eeMsecSinceBoot } |
This enumeration lists the available timestamp formats. More... | |
enum | teOutputFormats { eeFormatA, eeFormatB } |
This enumeration lists the available output formats. More... | |
enum | teGpioDirection { gnGpioInput = 0, gnGpioOutput = 1 } |
enum | teStepperSwitchPos { eeESTOP = 0, eeREV_STOP = 1, eeFWD_STOP = 2, eePOSITION1 = 3, eePOSITION2 = 4, eePOSITION3 = 5, eePOSITION4 = 6, eePOSITION5 = 7, eeNONE = 8 } |
enum | teStepperDir { eeFORWARD = 0, eeREVERSE = 1 } |
enum | teStepperCommand { eeSEEK = 0, eeGOTO = 1, eeMOVE = 2, eeIDLE = 3 } |
enum | teStepperMicroStepSize { eeFULL, eeHALF, eeONE_QUARTER, eeONE_EIGHTH, eeUNKNOWN } |
enum | teStepperCurrentLevel { eeCURRENT0, eeCURRENT1, eeCURRENT2, eeCURRENT3, eeUNKNOWNCURRENT } |
Variables | |
int | dsp_sdk_major = SDKMAJOR |
MityDSP SDK major version number (i.e. | |
int | dsp_sdk_minor = SDKMINOR |
MityDSP SDK minor version number (i.e. | |
int | dsp_sdk_build = SDKBUILD |
MityDSP SDK build version number (i.e. | |
const char * | dsp_sdk_str = "MityDSP SDK version " VSTR(SDKMAJOR) VDOT VSTR(SDKMINOR) VDOT VSTR(SDKBUILD) |
MityDSP SDK version as a string. | |
const char * | dsp_sdk_date = __DATE__ |
MityDSP SDK build date. | |
const char * | dsp_sdk_time = __TIME__ |
MityDSP SDK build time. | |
int | dsp_sdk_cgtools = __TI_COMPILER_VERSION__ |
Code Generation Tools revision used to build libraries. | |
int | dsp_core_lib_major = COREMAJOR |
MityDSP Core library major version number (i.e. | |
int | dsp_core_lib_minor = COREMINOR |
MityDSP Core library minor version number (i.e. | |
int | dsp_core_lib_build = COREBUILD |
MityDSP Core library build version number (i.e. | |
const char * | dsp_core_lib_str = "MityDSP core library version " VSTR(COREMAJOR) VDOT VSTR(COREMINOR) VDOT VSTR(COREBUILD) |
MityDSP Core library version as a string. | |
const char * | dsp_core_lib_date = __DATE__ |
MityDSP Core library build date. | |
const char * | dsp_core_lib_time = __TIME__ |
MityDSP Core library build time. | |
const unsigned int | gnCH0_MASK = 0x00000001 |
< Masks used to enable channels for round-robin capture | |
const unsigned int | gnCH1_MASK = 0x00000002 |
const unsigned int | gnCH2_MASK = 0x00000004 |
const unsigned int | gnCH3_MASK = 0x00000008 |
const unsigned int | gnCH4_MASK = 0x00000010 |
const unsigned int | gnCH5_MASK = 0x00000020 |
const unsigned int | gnCH6_MASK = 0x00000040 |
const unsigned int | gnCH7_MASK = 0x00000080 |
const unsigned int | FLASH_BANK_SIZE = 0x00100000 |
const unsigned int | IE_MASK_4 = 0x00000001 |
< Masks for global interrupt enables. | |
const unsigned int | IE_MASK_5 = 0x00000002 |
const unsigned int | IE_MASK_6 = 0x00000004 |
const unsigned int | IE_MASK_7 = 0x00000008 |
const int | GLOBAL_CORE_ID = 0 |
const int | MITY_UART_CORE_ID = 1 |
const int | ETHERNET_CORE_ID = 2 |
const int | HW_UART_CORE_ID = 3 |
const int | GPIO_CORE_ID = 4 |
const int | ADC9235_CORE_ID = 5 |
const int | SHIFT_REG_CORE_ID = 6 |
const int | I2C_CORE_ID = 7 |
const int | PWM_CORE_ID = 8 |
const int | STEPPER_CORE_ID = 9 |
const int | PULSE_INTEG_CORE_ID = 10 |
const int | ADC8343_CORE_ID = 11 |
const int | EVENT_CNTR_CORE_ID = 12 |
const int | TIMER_CORE_ID = 13 |
const int | SPI_CORE_ID = 14 |
const int | TMP05_CORE_ID = 15 |
const int | ADC8344_CORE_ID = 16 |
const int | RAM_BLOCK_CORE_ID = 17 |
const int | ADS8402_CORE_ID = 18 |
const int | AWG_CORE_ID = 19 |
const int | IIR_CORE_ID = 20 |
const int | TIME_GEN_CORE_ID = 21 |
const int | FPGA_DMA_CORE_ID = 22 |
const int | TOUCH_SCRN_CORE_ID = 23 |
const int | ADS8329_CORE_ID = 24 |
const int | QVGA_16_CORE_ID = 25 |
const int | LVDS_CORE_ID = 26 |
const int | CAMERALINK_CORE_ID = 27 |
const int | AD7760_CORE_ID = 28 |
const int | EZ_USB_CORE_ID = 29 |
const int | RFC1305_CLK_CORE_ID = 30 |
const int | LCD_EMIF_CORE_ID = 31 |
const int | DAC9881_CORE_ID = 32 |
const int | DUAL_AWG_CORE_ID = 33 |
const int | DCM_CTLR_CORE_ID = 34 |
const int | NUM_CORE_IDS = 35 |
const int | gnAutoLevel = -1 |
Indicates that automatic ISR level and vector installation should be attempted. | |
const unsigned int | gnGPIO_0 = 0x00000001 |
Mask for GPIO #0. | |
const unsigned int | gnGPIO_1 = 0x00000002 |
Mask for GPIO #1. | |
const unsigned int | gnGPIO_2 = 0x00000004 |
Mask for GPIO #2. | |
const unsigned int | gnGPIO_3 = 0x00000008 |
Mask for GPIO #3. | |
const unsigned int | gnGPIO_4 = 0x00000010 |
Mask for GPIO #4. | |
const unsigned int | gnGPIO_5 = 0x00000020 |
Mask for GPIO #5. | |
const unsigned int | gnGPIO_6 = 0x00000040 |
Mask for GPIO #6. | |
const unsigned int | gnGPIO_7 = 0x00000080 |
Mask for GPIO #7. | |
const unsigned int | gnGPIO_8 = 0x00000100 |
Mask for GPIO #8. | |
const unsigned int | gnGPIO_9 = 0x00000200 |
Mask for GPIO #9. | |
const unsigned int | gnGPIO_10 = 0x00000400 |
Mask for GPIO #10. | |
const unsigned int | gnGPIO_11 = 0x00000800 |
Mask for GPIO #11. | |
const unsigned int | gnGPIO_12 = 0x00001000 |
Mask for GPIO #12. | |
const unsigned int | gnGPIO_13 = 0x00002000 |
Mask for GPIO #13. | |
const unsigned int | gnGPIO_14 = 0x00004000 |
Mask for GPIO #14. | |
const unsigned int | gnGPIO_15 = 0x00008000 |
Mask for GPIO #15. | |
const unsigned int | gnGPIO_16 = 0x00010000 |
Mask for GPIO #16. | |
const unsigned int | gnGPIO_17 = 0x00020000 |
Mask for GPIO #17. | |
const unsigned int | gnGPIO_18 = 0x00040000 |
Mask for GPIO #18. | |
const unsigned int | gnGPIO_19 = 0x00080000 |
Mask for GPIO #19. | |
const unsigned int | gnGPIO_20 = 0x00100000 |
Mask for GPIO #20. | |
const unsigned int | gnGPIO_21 = 0x00200000 |
Mask for GPIO #21. | |
const unsigned int | gnGPIO_22 = 0x00400000 |
Mask for GPIO #22. | |
const unsigned int | gnGPIO_23 = 0x00800000 |
Mask for GPIO #23. | |
const unsigned int | gnGPIO_24 = 0x01000000 |
Mask for GPIO #24. | |
const unsigned int | gnGPIO_25 = 0x02000000 |
Mask for GPIO #25. | |
const unsigned int | gnGPIO_26 = 0x04000000 |
Mask for GPIO #26. | |
const unsigned int | gnGPIO_27 = 0x08000000 |
Mask for GPIO #27. | |
const unsigned int | gnGPIO_28 = 0x10000000 |
Mask for GPIO #28. | |
const unsigned int | gnGPIO_29 = 0x20000000 |
Mask for GPIO #29. | |
const unsigned int | gnGPIO_30 = 0x40000000 |
Mask for GPIO #30. | |
const unsigned int | gnGPIO_31 = 0x80000000 |
Mask for GPIO #31. | |
const unsigned int | gnGPIO_ALL = 0xFFFFFFFF |
Mask for all GPIOs. | |
const int | gnNumGpios = 32 |
Number of GPIO's available per instance. | |
const int | gnChainVector = -1 |
ISR should not be associated with a particular vector (i.e. | |
const int | Y2K = 2000 |
const int | UART_TX_FIFO_DEPTH = 64 |
Maximum depth of the UART internal TX FIFO. | |
PLL Registers | |
const unsigned int | PLL_PID = 0x01B7C000 |
Peripheral Identification Register. | |
const unsigned int | PLL_CSR = 0x01B7C100 |
Control/Status Register. | |
const unsigned int | PLL_MULT = 0x01B7C110 |
PLL Multiplier Control Register. | |
const unsigned int | PLL_DIV0 = 0x01B7C114 |
PLL Divider D0 Control Register. | |
const unsigned int | PLL_DIV1 = 0x01B7C118 |
PLL Divider D1 Control Register. | |
const unsigned int | PLL_DIV2 = 0x01B7C11C |
PLL Divider D2 Control Register. | |
const unsigned int | PLL_DIV3 = 0x01B7C120 |
PLL Divider D3 Control Register. | |
const unsigned int | OSC_DIV1 = 0x01B7C124 |
Oscillator Divider Control Register. | |
EMIF Registers | |
const unsigned int | EMIF_GCR = 0x1800000 |
Address of EMIF global control. | |
const unsigned int | EMIF_CE0 = 0x1800008 |
Address of EMIF CE0 control. | |
const unsigned int | EMIF_CE1 = 0x1800004 |
Address of EMIF CE1 control. | |
const unsigned int | EMIF_CE2 = 0x1800010 |
Address of EMIF CE2 control. | |
const unsigned int | EMIF_CE3 = 0x1800014 |
Address of EMIF CE3 control. | |
const unsigned int | EMIF_SDCTRL = 0x1800018 |
Address of EMIF SDRAM control. | |
const unsigned int | EMIF_SDRP = 0x180001c |
Address of EMIF SDRM refresh period. | |
const unsigned int | EMIF_SDEXT = 0x1800020 |
Address of EMIF SDRAM extension. |
typedef class tcDspAdc8343 MityDSP::tcDspAdc8344 |
< Also supports the ADS8344, so allow these names, too
typedef class tcDspAdc8343 MityDSP::tcDspAdc834x |
typedef void(* MityDSP::tfErrorCallback)(enum teErrorValues, const char *) |
Prototypes for the tcDspError callbacks.
typedef void(* MityDSP::tfLogCallback)(const char *, int, teErrorValues) |
typedef void(* MityDSP::tfMediaCallback)(bool, void *) |
typedef int(* MityDSP::tfIsrCallback)(Arg) |
Prototype for the tcDspInterruptDispatch ISR callback.
enum MityDSP::teFIFOLevel |
The teFIFOLevel enumeration defines the various FIFO levels that may be checked for the tcDspAdcBase class.
This enumeration lists the available message severities.
The value "none" cannot be used to create a message, it can only be used to set the filter level such that no tcDspError messages are created.
This enumeration lists the available output formats.
The defined formats are:
eeFormatA is the default format for backwards compatability.
const char * MityDSP::dsp_sdk_str = "MityDSP SDK version " VSTR(SDKMAJOR) VDOT VSTR(SDKMINOR) VDOT VSTR(SDKBUILD) |
MityDSP SDK version as a string.
const char * MityDSP::dsp_sdk_date = __DATE__ |
MityDSP SDK build date.
const char * MityDSP::dsp_sdk_time = __TIME__ |
MityDSP SDK build time.
int MityDSP::dsp_sdk_cgtools = __TI_COMPILER_VERSION__ |
Code Generation Tools revision used to build libraries.
int MityDSP::dsp_core_lib_major = COREMAJOR |
MityDSP Core library major version number (i.e.
x in x.y.z).
int MityDSP::dsp_core_lib_minor = COREMINOR |
MityDSP Core library minor version number (i.e.
y in x.y.z).
int MityDSP::dsp_core_lib_build = COREBUILD |
MityDSP Core library build version number (i.e.
z in x.y.z).
const char * MityDSP::dsp_core_lib_str = "MityDSP core library version " VSTR(COREMAJOR) VDOT VSTR(COREMINOR) VDOT VSTR(COREBUILD) |
MityDSP Core library version as a string.
const char * MityDSP::dsp_core_lib_date = __DATE__ |
MityDSP Core library build date.
const char * MityDSP::dsp_core_lib_time = __TIME__ |
MityDSP Core library build time.
const unsigned int MityDSP::gnCH0_MASK = 0x00000001 |
< Masks used to enable channels for round-robin capture
const unsigned int MityDSP::gnCH1_MASK = 0x00000002 |
const unsigned int MityDSP::gnCH2_MASK = 0x00000004 |
const unsigned int MityDSP::gnCH3_MASK = 0x00000008 |
const unsigned int MityDSP::gnCH4_MASK = 0x00000010 |
const unsigned int MityDSP::gnCH5_MASK = 0x00000020 |
const unsigned int MityDSP::gnCH6_MASK = 0x00000040 |
const unsigned int MityDSP::gnCH7_MASK = 0x00000080 |
const unsigned int MityDSP::FLASH_BANK_SIZE = 0x00100000 |
const unsigned int MityDSP::PLL_PID = 0x01B7C000 |
Peripheral Identification Register.
const unsigned int MityDSP::PLL_CSR = 0x01B7C100 |
Control/Status Register.
const unsigned int MityDSP::PLL_MULT = 0x01B7C110 |
PLL Multiplier Control Register.
const unsigned int MityDSP::PLL_DIV0 = 0x01B7C114 |
PLL Divider D0 Control Register.
const unsigned int MityDSP::PLL_DIV1 = 0x01B7C118 |
PLL Divider D1 Control Register.
const unsigned int MityDSP::PLL_DIV2 = 0x01B7C11C |
PLL Divider D2 Control Register.
const unsigned int MityDSP::PLL_DIV3 = 0x01B7C120 |
PLL Divider D3 Control Register.
const unsigned int MityDSP::OSC_DIV1 = 0x01B7C124 |
Oscillator Divider Control Register.
const unsigned int MityDSP::EMIF_GCR = 0x1800000 |
Address of EMIF global control.
const unsigned int MityDSP::EMIF_CE0 = 0x1800008 |
Address of EMIF CE0 control.
const unsigned int MityDSP::EMIF_CE1 = 0x1800004 |
Address of EMIF CE1 control.
const unsigned int MityDSP::EMIF_CE2 = 0x1800010 |
Address of EMIF CE2 control.
const unsigned int MityDSP::EMIF_CE3 = 0x1800014 |
Address of EMIF CE3 control.
const unsigned int MityDSP::EMIF_SDCTRL = 0x1800018 |
Address of EMIF SDRAM control.
const unsigned int MityDSP::EMIF_SDRP = 0x180001c |
Address of EMIF SDRM refresh period.
const unsigned int MityDSP::EMIF_SDEXT = 0x1800020 |
Address of EMIF SDRAM extension.
const unsigned int MityDSP::IE_MASK_4 = 0x00000001 |
< Masks for global interrupt enables.
const unsigned int MityDSP::IE_MASK_5 = 0x00000002 |
const unsigned int MityDSP::IE_MASK_6 = 0x00000004 |
const unsigned int MityDSP::IE_MASK_7 = 0x00000008 |
const int MityDSP::GLOBAL_CORE_ID = 0 |
const int MityDSP::MITY_UART_CORE_ID = 1 |
const int MityDSP::ETHERNET_CORE_ID = 2 |
const int MityDSP::HW_UART_CORE_ID = 3 |
const int MityDSP::GPIO_CORE_ID = 4 |
const int MityDSP::ADC9235_CORE_ID = 5 |
const int MityDSP::SHIFT_REG_CORE_ID = 6 |
const int MityDSP::I2C_CORE_ID = 7 |
const int MityDSP::PWM_CORE_ID = 8 |
const int MityDSP::STEPPER_CORE_ID = 9 |
const int MityDSP::PULSE_INTEG_CORE_ID = 10 |
const int MityDSP::ADC8343_CORE_ID = 11 |
const int MityDSP::EVENT_CNTR_CORE_ID = 12 |
const int MityDSP::TIMER_CORE_ID = 13 |
const int MityDSP::SPI_CORE_ID = 14 |
const int MityDSP::TMP05_CORE_ID = 15 |
const int MityDSP::ADC8344_CORE_ID = 16 |
const int MityDSP::RAM_BLOCK_CORE_ID = 17 |
const int MityDSP::ADS8402_CORE_ID = 18 |
const int MityDSP::AWG_CORE_ID = 19 |
const int MityDSP::IIR_CORE_ID = 20 |
const int MityDSP::TIME_GEN_CORE_ID = 21 |
const int MityDSP::FPGA_DMA_CORE_ID = 22 |
const int MityDSP::TOUCH_SCRN_CORE_ID = 23 |
const int MityDSP::ADS8329_CORE_ID = 24 |
const int MityDSP::QVGA_16_CORE_ID = 25 |
const int MityDSP::LVDS_CORE_ID = 26 |
const int MityDSP::CAMERALINK_CORE_ID = 27 |
const int MityDSP::AD7760_CORE_ID = 28 |
const int MityDSP::EZ_USB_CORE_ID = 29 |
const int MityDSP::RFC1305_CLK_CORE_ID = 30 |
const int MityDSP::LCD_EMIF_CORE_ID = 31 |
const int MityDSP::DAC9881_CORE_ID = 32 |
const int MityDSP::DUAL_AWG_CORE_ID = 33 |
const int MityDSP::DCM_CTLR_CORE_ID = 34 |
const int MityDSP::NUM_CORE_IDS = 35 |
const int MityDSP::gnAutoLevel = -1 |
Indicates that automatic ISR level and vector installation should be attempted.
const unsigned int MityDSP::gnGPIO_0 = 0x00000001 |
Mask for GPIO #0.
const unsigned int MityDSP::gnGPIO_1 = 0x00000002 |
Mask for GPIO #1.
const unsigned int MityDSP::gnGPIO_2 = 0x00000004 |
Mask for GPIO #2.
const unsigned int MityDSP::gnGPIO_3 = 0x00000008 |
Mask for GPIO #3.
const unsigned int MityDSP::gnGPIO_4 = 0x00000010 |
Mask for GPIO #4.
const unsigned int MityDSP::gnGPIO_5 = 0x00000020 |
Mask for GPIO #5.
const unsigned int MityDSP::gnGPIO_6 = 0x00000040 |
Mask for GPIO #6.
const unsigned int MityDSP::gnGPIO_7 = 0x00000080 |
Mask for GPIO #7.
const unsigned int MityDSP::gnGPIO_8 = 0x00000100 |
Mask for GPIO #8.
const unsigned int MityDSP::gnGPIO_9 = 0x00000200 |
Mask for GPIO #9.
const unsigned int MityDSP::gnGPIO_10 = 0x00000400 |
Mask for GPIO #10.
const unsigned int MityDSP::gnGPIO_11 = 0x00000800 |
Mask for GPIO #11.
const unsigned int MityDSP::gnGPIO_12 = 0x00001000 |
Mask for GPIO #12.
const unsigned int MityDSP::gnGPIO_13 = 0x00002000 |
Mask for GPIO #13.
const unsigned int MityDSP::gnGPIO_14 = 0x00004000 |
Mask for GPIO #14.
const unsigned int MityDSP::gnGPIO_15 = 0x00008000 |
Mask for GPIO #15.
const unsigned int MityDSP::gnGPIO_16 = 0x00010000 |
Mask for GPIO #16.
const unsigned int MityDSP::gnGPIO_17 = 0x00020000 |
Mask for GPIO #17.
const unsigned int MityDSP::gnGPIO_18 = 0x00040000 |
Mask for GPIO #18.
const unsigned int MityDSP::gnGPIO_19 = 0x00080000 |
Mask for GPIO #19.
const unsigned int MityDSP::gnGPIO_20 = 0x00100000 |
Mask for GPIO #20.
const unsigned int MityDSP::gnGPIO_21 = 0x00200000 |
Mask for GPIO #21.
const unsigned int MityDSP::gnGPIO_22 = 0x00400000 |
Mask for GPIO #22.
const unsigned int MityDSP::gnGPIO_23 = 0x00800000 |
Mask for GPIO #23.
const unsigned int MityDSP::gnGPIO_24 = 0x01000000 |
Mask for GPIO #24.
const unsigned int MityDSP::gnGPIO_25 = 0x02000000 |
Mask for GPIO #25.
const unsigned int MityDSP::gnGPIO_26 = 0x04000000 |
Mask for GPIO #26.
const unsigned int MityDSP::gnGPIO_27 = 0x08000000 |
Mask for GPIO #27.
const unsigned int MityDSP::gnGPIO_28 = 0x10000000 |
Mask for GPIO #28.
const unsigned int MityDSP::gnGPIO_29 = 0x20000000 |
Mask for GPIO #29.
const unsigned int MityDSP::gnGPIO_30 = 0x40000000 |
Mask for GPIO #30.
const unsigned int MityDSP::gnGPIO_31 = 0x80000000 |
Mask for GPIO #31.
const unsigned int MityDSP::gnGPIO_ALL = 0xFFFFFFFF |
Mask for all GPIOs.
const int MityDSP::gnNumGpios = 32 |
Number of GPIO's available per instance.
const int MityDSP::gnChainVector = -1 |
ISR should not be associated with a particular vector (i.e.
it should be chained).
const int MityDSP::Y2K = 2000 |
const int MityDSP::UART_TX_FIFO_DEPTH = 64 |
Maximum depth of the UART internal TX FIFO.