Instances of this class handle access to a "generic" implementation of the SPI interface for the MityDSP. More...
#include <core/DspSpi.h>
Classes | |
union | tuFifoData |
The tuFifoData union defines the data bits sent to or received from the SPI FIFOs. More... |
Public Types | |
enum | teFIFOLevel { eeEmpty = 0, eeOneQ = 1, eeHalf = 2, eeThreeQ = 3, eeFull = 4, eeAll = 5 } |
The teFIFOLevel enumeration defines the various FIFO levels that may be checked for the tcDspSpi class. More... | |
enum | teFIFOWidth { ee4Bit = 0, ee8Bit = 1, ee12Bit = 2, ee16Bit = 3, ee20Bit = 4, ee24Bit = 5, ee28Bit = 6, ee32Bit = 7 } |
The teFIFOWidth enumeration defines the width of the data being written to the MOSI FIFO, or read from the MISO FIFO. More... | |
enum | teClockEdge { eeFalling, eeRising } |
The teClockEdge enumeration defines the edges used by the TX or RX clock to read data. More... | |
typedef void(* | tfIsrCallback )(tcDspSpi *) |
prototype for the ISR callbacks. | |
typedef void(* | tfIsrCallbackWithArg )(tcDspSpi *, void *) |
Public Member Functions | |
tcDspSpi (void *apAddress, int anLevel=gnAutoLevel, LCK_Handle ahLock=NULL) | |
This constructor is used to open an istance of the DspSpi interface. | |
~tcDspSpi () | |
This destructor is used to close up and free the resources tied to the associated SPI interface. | |
bool | SetFifoWidth (teFIFOWidth aeWidth) |
Sets the data width for the SPI bus. | |
teFIFOWidth | GetFifoWidth (void) |
Gets the current data width for the SPI bus. | |
void | SetTxClockEdge (teClockEdge aeEdge) |
Sets the transmit clock edge to use for writing data. | |
teClockEdge | GetTxClockEdge (void) |
Gets the transmit clock edge used for writing data. | |
void | SetRxClockEdge (teClockEdge aeEdge) |
Sets the receive clock edge to use for reading data. | |
teClockEdge | GetRxClockEdge (void) |
Gets the receive clock edge used for reading data. | |
void | SetClockGateWithSync (bool abGate) |
Sets the clock gating state. | |
bool | GetClockGateWithSync (void) |
Gets the clock gating state. | |
bool | GetTxFIFOLevel (teFIFOLevel aeLevel) |
Gets transmit FIFO Level flag. | |
unsigned short | GetTxFIFOLevel (void) |
Gets transmit FIFO Level. | |
bool | GetRxFIFOLevel (teFIFOLevel aeLevel) |
Gets receive FIFO Level flag. | |
unsigned short | GetRxFIFOLevel (void) |
Gets receive FIFO Level. | |
void | SetTxFIFOInterruptLevel (bool abEnable, teFIFOLevel aeLevel=eeAll) |
Sets the transmit FIFO interrupt based on the level specified. | |
void | RegisterTxFIFOHandler (tfIsrCallback afCallback, teFIFOLevel aeLevel=eeAll) |
Registers the specified ISR callback for the specified transmit FIFO level interrupt. | |
void | RegisterTxFIFOHandler (tfIsrCallbackWithArg afCallback, void *apUserArg=NULL, teFIFOLevel aeLevel=eeAll) |
Registers the specified ISR callback for the specified transmit FIFO level interrupt. | |
int | WriteData (tuFifoData *apData, int anCount, tcDspOutputLatch *apLatch=NULL, unsigned int anLatchID=0) |
Writes data to the SPI TX FIFO. | |
unsigned int | GetTxFIFODepth (void) |
Returns the depth (in 24-bit words) of the transmit FIFO. | |
int | ReadData (tuFifoData *apData, int anCount, tcDspOutputLatch *apLatch=NULL, unsigned int anLatchID=0) |
Reads data from the SPI RX FIFO. | |
unsigned int | GetRxFIFODepth (void) |
Returns the depth (in 24-bit words) of the receive FIFO. | |
bool | DrainRxFIFO (void) |
This routine will drain the SPI interface read FIFO. |
Static Public Member Functions | |
static int | interrupt_dispatch (Arg arMyObject) |
Static interrupt dispatch routine. |
Public Attributes | |
unsigned int | mnInterruptCount |
ISR counter (debug). |
Protected Member Functions | |
void | spiInterrupt (void) |
Interrupt service routine for the SPI class. |
Protected Attributes | |
LCK_Handle | mhMutexLock |
To serialize access. | |
SEM_Handle | mhTransmitComplete |
Notes when a transmission is done. | |
unsigned int | mnRxFifoDepth |
depth of firmware RX FIFO. | |
unsigned int | mnTxFifoDepth |
depth of firmware TX FIFO. | |
tfIsrCallback | mfTxIsrCallback [gnNUM_INT_LEVELS] |
tfIsrCallbackWithArg | mfTxIsrCallbackWithArg [gnNUM_INT_LEVELS] |
void * | mpTxUserArg [gnNUM_INT_LEVELS] |
bool | mbUserTxComplete |
user has asked for TX complete interrupt | |
unsigned int | mnLastLatch |
ID of last enabled latch. | |
volatile unsigned int * | mpBaseAddr |
firmware base address. | |
volatile unsigned int * | mpRxFifo |
pointer to SPI RX FIFO. | |
volatile unsigned int * | mpTxFifo |
pointer to SPI TX FIFO. | |
unsigned short | mnMyIntMask |
core interrupt mask. | |
int | mnMyIntLevel |
core interrupt level. | |
int | mnMyIntVector |
core interrupt vector. |
Static Protected Attributes | |
static const int | gnNUM_INT_LEVELS = 4 |
valid TX FIFO interrupt levels | |
static const int | gnRX_TIMEOUT_COUNT = 100000 |
attempts to find RX FIFO not empty |
Instances of this class handle access to a "generic" implementation of the SPI interface for the MityDSP.
typedef void(* MityDSP::tcDspSpi::tfIsrCallback)(tcDspSpi *) |
prototype for the ISR callbacks.
typedef void(* MityDSP::tcDspSpi::tfIsrCallbackWithArg)(tcDspSpi *, void *) |
The teFIFOLevel enumeration defines the various FIFO levels that may be checked for the tcDspSpi class.
The teFIFOWidth enumeration defines the width of the data being written to the MOSI FIFO, or read from the MISO FIFO.
tcDspSpi::tcDspSpi | ( | void * | apAddress, |
int | anLevel = gnAutoLevel , |
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LCK_Handle | ahLock = NULL |
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This constructor is used to open an istance of the DspSpi interface.
[in] | apAddress | Base Address of SPI core |
[in] | anLevel | Optional parameter to force a chained interrupt at the specified level. |
[in] | ahLock | Optional parameter specifying a lock to use to protect SPI writes. |
tcDspSpi::~tcDspSpi | ( | ) |
This destructor is used to close up and free the resources tied to the associated SPI interface.
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Static interrupt dispatch routine.
Required because of the hidden this pointer associated with a member function, which cannot be passed directly to the interrupt dispatcher.
[in] | ahMyObject | The "this->" pointer for the instance of tcDspSpi associated with this ISR. |
bool tcDspSpi::SetFifoWidth | ( | teFIFOWidth | aeWidth | ) |
Sets the data width for the SPI bus.
The FIFO's remain 32-bits wide, but only the specified LSBs are valid for transmit or receive.
[in] | aeWidth | Enumeration representing SPI width (up to 32-bits). |
tcDspSpi::teFIFOWidth tcDspSpi::GetFifoWidth | ( | void | ) |
Gets the current data width for the SPI bus.
void tcDspSpi::SetTxClockEdge | ( | teClockEdge | aeEdge | ) |
Sets the transmit clock edge to use for writing data.
[in] | aeEdge | Enumeration representing rising or falling edge. |
tcDspSpi::teClockEdge tcDspSpi::GetTxClockEdge | ( | void | ) |
Gets the transmit clock edge used for writing data.
void tcDspSpi::SetRxClockEdge | ( | teClockEdge | aeEdge | ) |
Sets the receive clock edge to use for reading data.
[in] | aeEdge | Enumeration representing rising or falling edge. |
tcDspSpi::teClockEdge tcDspSpi::GetRxClockEdge | ( | void | ) |
Gets the receive clock edge used for reading data.
void tcDspSpi::SetClockGateWithSync | ( | bool | abGate | ) |
Sets the clock gating state.
If true, the clock is gated by the SYNC signal.
[in] | abGate | Set to true to gate the clock with sync. |
bool tcDspSpi::GetClockGateWithSync | ( | void | ) |
bool tcDspSpi::GetTxFIFOLevel | ( | teFIFOLevel | anLevel | ) |
Gets transmit FIFO Level flag.
[in] | anLevel | The level to check |
unsigned short tcDspSpi::GetTxFIFOLevel | ( | void | ) |
bool tcDspSpi::GetRxFIFOLevel | ( | teFIFOLevel | anLevel | ) |
Gets receive FIFO Level flag.
[in] | anLevel | The level to check |
unsigned short tcDspSpi::GetRxFIFOLevel | ( | void | ) |
Gets receive FIFO Level.
void tcDspSpi::SetTxFIFOInterruptLevel | ( | bool | abEnable, |
teFIFOLevel | aeLevel = eeAll |
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Sets the transmit FIFO interrupt based on the level specified.
[in] | abEnable | True to enable level interrupt. False to disable. |
[in] | aeLevel | The desired FIFO level interrupt (default: eeAll) |
void tcDspSpi::RegisterTxFIFOHandler | ( | tfIsrCallback | afCallback, |
teFIFOLevel | aeLevel = eeAll |
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Registers the specified ISR callback for the specified transmit FIFO level interrupt.
A separate callback may be provided for each of the .four valid TX interrupt levels.
[in] | afCallback | The callback to associate with the interrupt (or NULL for none). |
[in] | aeLevel | The desired FIFO level interrupt (default: eeAll) |
void tcDspSpi::RegisterTxFIFOHandler | ( | tfIsrCallbackWithArg | afCallback, |
void * | apUserArg = NULL , |
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teFIFOLevel | aeLevel = eeAll |
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Registers the specified ISR callback for the specified transmit FIFO level interrupt.
A separate callback may be provided for each of the .four valid TX interrupt levels. The callback may have a user-supplied argument.
[in] | afCallback | The callback to associate with the interrupt (or NULL for none). |
[in] | apUserArg | An argument to be supplied with the callback. |
[in] | aeLevel | The desired FIFO level interrupt (default: eeAll) |
int tcDspSpi::WriteData | ( | tuFifoData * | apData, |
int | anCount, | ||
tcDspOutputLatch * | apLatch = NULL , |
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unsigned int | anLatchID = 0 |
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) |
Writes data to the SPI TX FIFO.
Access is serialized via a mutex. An optional latch may be provided if it is necessary to select an individual device on the bus. The function may also be asked to wait for the TX FIFO to empty before the latch is asserted and the new data is written. This allows SPI activity to one device to complete before the next device is selected.
[in] | apData | Pointer to data to send to the TX FIFO |
[in] | anCount | Number of tuFifoData entries to send |
[in] | apLatch | An optional pointer to a latch class (default:NULL) |
[in] | anLatchID | Latch ID to assert for this device, if any (default:0) |
unsigned int tcDspSpi::GetTxFIFODepth | ( | void | ) |
Returns the depth (in 24-bit words) of the transmit FIFO.
int tcDspSpi::ReadData | ( | tuFifoData * | apData, |
int | anCount, | ||
tcDspOutputLatch * | apLatch = NULL , |
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unsigned int | anLatchID = 0 |
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Reads data from the SPI RX FIFO.
Access is serialized via a mutex. Since the MityDSP is the master device, a "dummy" transmit is required to clock the slave device. This transmit will handle any latch changes, including waiting for a transmit to another device to complete.
[in] | apData | Pointer to storage for data read from the RX FIFO. |
[in] | anCount | Number of tuFifoData entries to read. |
[in] | apLatch | An optional pointer to a latch class (default:NULL) |
[in] | anLatchID | Latch ID to assert for this device, if any (default:0) |
unsigned int tcDspSpi::GetRxFIFODepth | ( | void | ) |
Returns the depth (in 24-bit words) of the receive FIFO.
bool tcDspSpi::DrainRxFIFO | ( | void | ) |
This routine will drain the SPI interface read FIFO.
It is useful when a clearing operation is require or after initialization.
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Interrupt service routine for the SPI class.
The ISR reads and clears any pending interrupts. If any of the pending interrupts has a callback registered for it, the routine is called.
"Interrupt-ness" is taken care of by the 'dispatcher' in DSP/BIOS. Installed by the constructor.
unsigned int MityDSP::tcDspSpi::mnInterruptCount |
ISR counter (debug).
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valid TX FIFO interrupt levels
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attempts to find RX FIFO not empty
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To serialize access.
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Notes when a transmission is done.
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depth of firmware RX FIFO.
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depth of firmware TX FIFO.
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user has asked for TX complete interrupt
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ID of last enabled latch.
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firmware base address.
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pointer to SPI RX FIFO.
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pointer to SPI TX FIFO.
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core interrupt mask.
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core interrupt level.
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core interrupt vector.