The tcDspGpio class may be used to provide access to a single GPIO core. Each instance of DspGpio provides access to 32 GPIO pins, and installs an ISR at the specified interrupt level to report changes in values (rising or falling edge) for any input pins thus configured.
When created, the constructor requires a valid base address for the GPIO core. Individual pin direction, interrupt enables, and semaphores used to count interrupts are all set via the configurePins method.
Current pin values are retrieved via readPins. These represent the values currently being read/written for each pin.
Current pin values are set via writePins. For pins configured as output, these values are immediately implemented. For pins configured as input, these values become the defaults used if/when the pin is ever reconfigured as an output (used to avoid glitches prior to enabling an output).
There is no limit to the number of instances of tcDspGpio that may be created.
An instance of the tcDspGpio class is created by specifying the firmware base address of the core and the interrupt level used. This core supports specifying a level of gnAutoLevel (which is the default if no level is provided), which automatically installs a vectored interrupt.
This is a simple example of tcDspGpio creation and usage: