The tcDspRamBlock class is used to provide a consistent interface to simple MityDSP core firmware. The interface has 16 input and output registers, of either 8/16/24/32 bits in width. Each register supports a "dirty bit" in a separate register which can be used to communicate between the firmware and software that new data is available. Finally, the interface supports an interrupt mode, which can be used to indicate when new data is available for reading.
Different cores may use different subsets of the functionality available in the tcDspRamBlock base class. Even if they are input-only, or output-only, or used only 1 of the 16 available blocks, they still adhere to this same basic interface.
An instance of the tcDspRamBlock class is created by specifying the firmware base address of the firmware core and the interrupt level used. This core supports specifying a level of gnAutoLevel, which automatically installs a vectored interrupt.
Usage examples are included in the specific classes that derive from this base class.