Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

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-- You must compile the wrapper file Sine_generator.vhd when simulating

-- the core, Sine_generator. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

LIBRARY XilinxCoreLib;

-- synthesis translate_on

ENTITY Sine_generator IS

  PORT (

    aclk : IN STD_LOGIC;

    aclken : IN STD_LOGIC;

    aresetn : IN STD_LOGIC;

    m_axis_data_tvalid : OUT STD_LOGIC;

    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

  );

END Sine_generator;

ARCHITECTURE Sine_generator_a OF Sine_generator IS

-- synthesis translate_off

COMPONENT wrapped_Sine_generator

  PORT (

    aclk : IN STD_LOGIC;

    aclken : IN STD_LOGIC;

    aresetn : IN STD_LOGIC;

    m_axis_data_tvalid : OUT STD_LOGIC;

    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

  );

END COMPONENT;

-- Configuration specification

  FOR ALL : wrapped_Sine_generator USE ENTITY XilinxCoreLib.dds_compiler_v5_0(behavioral)

    GENERIC MAP (

      c_accumulator_width => 12,

      c_amplitude => 0,

      c_chan_width => 1,

      c_channels => 1,

      c_debug_interface => 0,

      c_has_aclken => 1,

      c_has_aresetn => 1,

      c_has_channel_index => 0,

      c_has_m_data => 1,

      c_has_m_phase => 0,

      c_has_phase_out => 0,

      c_has_phasegen => 1,

      c_has_s_config => 0,

      c_has_s_phase => 0,

      c_has_sincos => 1,

      c_has_tlast => 0,

      c_has_tready => 0,

      c_latency => 6,

      c_m_data_has_tuser => 0,

      c_m_data_tdata_width => 16,

      c_m_data_tuser_width => 1,

      c_m_phase_has_tuser => 0,

      c_m_phase_tdata_width => 1,

      c_m_phase_tuser_width => 1,

      c_mem_type => 1,

      c_negative_cosine => 0,

      c_negative_sine => 0,

      c_noise_shaping => 0,

      c_optimise_goal => 0,

      c_output_width => 12,

      c_outputs_required => 0,

      c_phase_angle_width => 12,

      c_phase_increment => 2,

      c_phase_increment_value => "10000,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",

      c_phase_offset => 0,

      c_phase_offset_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",

      c_por_mode => 0,

      c_s_config_sync_mode => 0,

      c_s_config_tdata_width => 1,

      c_s_phase_has_tuser => 0,

      c_s_phase_tdata_width => 1,

      c_s_phase_tuser_width => 1,

      c_use_dsp48 => 0,

      c_xdevicefamily => "spartan6"

    );

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_Sine_generator

  PORT MAP (

    aclk => aclk,

    aclken => aclken,

    aresetn => aresetn,

    m_axis_data_tvalid => m_axis_data_tvalid,

    m_axis_data_tdata => m_axis_data_tdata

  );

-- synthesis translate_on

END Sine_generator_a;