Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi,

I have a custom board with
1) MityDspl-138F module (with FPGA)
2) No Ethernet port
3) UART,USB,SD CARD interface
4) We are using ADC5560 and DAC5672, reference is taken from Analog Expansion Board.
ADC and DAC both operates on 40MHz.
5) we have used uPP interface in our end application.

we have done following steps till date.

1) I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.

2) Invidually tested ADC and DAC examples.

3) We took reference of ADC and DAC test examples and built the application which takes real time analog data from signal generator and check output on the scope. It gives output frequency on scope as input frequency, but there is a gap in between output waveform of 6ms. The waveform appears for 1ms. so , it is like 1 ms signal and 6ms no output.

I have following queries.

1) From the FPGA program ( from MityDSP) it seems , it gives 50MHZ clock to uPP interface receive channel. It means ADC is giving samples at 40MHZ and uPP receive channel reads it at 50MHz. Is it correct?

2) In our real time application, we have input buffer of 32000*16 bit (reference from MityDSP ADC example) and output buffer is also 32000*16 bit (reference from MityDSP DAC example). As per my understaning we can not have buffer which is more than 64000*8 bit (32000*16 bit), as there is a limitation of programming window size which is (1-7FFFh) for uPP DMA Channel Descriptor Register( Reference - uPP user's guide). We have linecnt of 1 (reference from MityDSP ADC example) for uPP DMA Channel Descriptor Register.

Can we have LNCNT more then 1 and each line have maximum window size of 64000 * 8 bits?

3) As I mentioned above , in our real time application we have output waveform with 1ms output waveform and 6ms no output. Now if i reduced the input buffer from 32000*16 bits to 16000*16 bits and also output buffer from 32000*16 bits to 16000*16 bits. Then the output is also affected and gives waveform for 500us and no output for 3ms. It looks the off period is the time where uPP interface reads data at receive channel. As per my understading, on transmit side once we program uPP DMA register,the rest of the things will be taken care by uPP DMA engine and DSP is free to do other task. So,these two process 1) data transmission from output buffer to uPP FIFO should be done by DMA (after programing uPP DMA registers)and 2) DSP reads data from the input buffer should be done at the same time. If it is so, why it is giving output off for some time? Is it because the buffer is in DDR2 RAM? Could it take more time to read or write from DDR2 RAM? Please suggest some work around, as we need contineous output.

4) In uPP interface, I belive transmission and receiving can be done at the same time as one channel is for receiving and the other one is for transmission. Is that correct?

5) we have also problem for lower frequencies, as we received more samples for lower frequencies and buffer is only 64000 * 8, which is not enough to generate even one cycle for lower frequencies. Please suggest.

Thanks,
- Vivek