Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

(posted on behalf of a customer)

I have a question about the FPGA I/O bandwidth coming off expansion headers 2 & 3 on the development kit. I would like to interface the FPGA to data converters and need to know the sampling rate limitations imposed by the Molex 79109-1224 connectors to the FPGA on the MityDSP-L138F module. I found min/max limit of 20/68MHz in the data sheet for the Profibus development kit. This was for the MDK-8 Digital I/O interface and I didn't know if this is the same as the FPGA I/O. Can you please tell me the recommended maximum single-ended and/or differential signal rates for the FPGA I/O to the expansion headers?