What‘s the configuration mode of the FPGA？
Added by Yueqiang Lu over 12 years ago
Hello,
We are using the MityDsp-L138F board. I want to know the FPGA's configuration mode on the board, is it MASTER SPI,BPI or slave SPI ,BPI? We can find nothing about pin M0&M1 of FPGA in the datasheets.
Anybody can tell me?
Thanks.
Replies (5)
RE: What‘s the configuration mode of the FPGA？ - Added by Michael Williamson over 12 years ago
Hello Mr. Lu,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor. The wiki has a section about programming the device using either uBoot or Linux drivers. While unconfigured the FPGA will tristate the IO pins.
-Mike
RE: What‘s the configuration mode of the FPGA？ - Added by Yueqiang Lu over 12 years ago
Thanks very much.
RE: What‘s the configuration mode of the FPGA？ - Added by Yueqiang Lu over 12 years ago
Hello Mike，
I still have a question. I found out in the MityDSP-L138F Carrier Board Design Guide that you connected the pin EMA_WE/GP311 of L138 to CCLK pin of FPGA. But the FPGA configuration document suggests DSP's CLOCK pin connects to FPGA's CCLK in slave mode.
So I want to know if your data sheet MityDSP-L138F Carrier Board Design Guide is written wrong.(The specific chapter is 3.4 OMAP-L138 pin out)
Thank you.
RE: What‘s the configuration mode of the FPGA？ - Added by Michael Williamson over 12 years ago
The EMA_WE (B9) pin of the OMAP-L138 is connected to the CCLK (R15) pin on the FPGA for slave select configuration. The WE pin is used during the EMIFA write cycle as a controlled clock to drive the FPGA CCLK during configuration while the proper configuration byte is present on the data bus. CCLK is not intended for use as a general purpose / higher speed clock pin; GCLK pins should be used as they have a dedicate path to the clock buffers within the fabric.
The EMA_CLK (B7) pin of the OMAP-L138 is connected to GCLK30 (T8) pin on the FPGA for clocked interfacing with the processor via the EMIFA after the FPGA has been configured. This clock line is what is used for EMIFA interfacing and as a general clock for the FPGA to use. You can also provide other clocks externally to the FPGA via the edge connector GCLK connected pins.
The CLKOUT pin (T18) of the OMAP-L138 is also connected to the FPGA on pin J7, but this is not a GCLK pin (we didn't have the routing resources to get it to a GCLK pin) and you may have some skew / latency issues to sort out if you want to use this for any I/O between the FPGA and the DSP. It would, however, be fine to use to source an independent clock connection to the FPGA as the EMA_CLK pin will vary if you alter the CPU frequency during runtime (see the OMAP-L138 TRM regarding the clocking design for more information). We typically do not use this connection in designs here, but the clock connection is available.
The table in section 3.4 of the Design Guide seems consistent with this, and I do not see an error. Can you be more specific as to where you see the error?
-Mike
RE: What‘s the configuration mode of the FPGA？ - Added by Yueqiang Lu over 12 years ago
Ok, Maybe I see.
FPGA's pin CCLK is the configuration clock , but it has two modes , namely Continuous data loading and Non-continuous data loading.
Maybe you choose the later one, right?
I originally think that the FPGA CCLK need only a continuous clock . But the DSP EMA_WE (B9)pin is a write enable pin but not a clock out pin, that's what confuesd me so much.
I'm a tyro in hardware design. Sorry to trouble you so much.
Thanks.
