Project

General

Profile

Programming FPGA on power up.

Added by Rex Taylor almost 9 years ago

Hello

We have been trying to save our .bin file to flash and load the FPGA on power up of our MityDSP.

Our board details are:-
U-Boot > factoryconfig
Factory Configuration:
Config Version : 1.1
MAC Address : 00:50:C2:E6:76:74
Serial Number : 120189
FPGA Type : 4 [XC6SLX45]
Part Number : L138-FI-225-RC
U-Boot >

On booting we get the following
OMAP-L138/AM-1808/AM-1810 initialization passed!
Configuring 128MB mDDR
Booting TI User Boot Loader
UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53
UBL Flashtype: SPI
Starting SPI Memory Copy...
Valid magicnum, 0x55424CBB, found at offset 0x00010000.
DONE
Jumping to entry point at 0xC1080000.

U-Boot 2009.11-dirty (Apr 04 2012 - 13:01:11)

I2C: ready
DRAM: 128 MB
NAND: 256 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 0
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]

Hit any key to stop autoboot: 0
8192 KiB M25P64 at 0:0 is now current device
Loading FPGA from 0xC0700000 with 0x16A78C bytes
Loading FPGA done
U-Boot >

But the 3 leds (BUSY, DONE and AWAKE) do not light up.

The .bin file I have saved to flash is IndustrialIO.bin from this link:- http://support.criticallink.com/redmine/boards/12/topics/604

We tried 'loadfpga' as follows

U-Boot > tftp 0xc0780000 192.168.0.155:IndustrialIO.bin
Using device
TFTP from server 192.168.0.155; our IP address is 192.168.0.156
Filename 'IndustrialIO.bin'.
Load address: 0xc0780000
Loading: ################################################################# #####################################
done
Bytes transferred = 1484404 (16a674 hex)
U-Boot > loadfpga 0xc0700000 0x16a674
Loading FPGA from 0xC0700000 with 0x16A674 bytes
Loading FPGA done
U-Boot >

as well as

tftp 0xc0780000 192.168.0.155:IndustrialIO.bin
Using device
TFTP from server 192.168.0.155; our IP address is 192.168.0.156
Filename 'IndustrialIO.bin'.
Load address: 0xc0780000
Loading: ################################################################# #####################################
done
Bytes transferred = 1484404 (16a674 hex)
U-Boot > sf probe 0
8192 KiB M25P64 at 0:0 is now current device
U-Boot > sf erase 0x580000 0x170000
U-Boot > sf write 0xc0700000 0x580000 0x16a674
U-Boot >

and our environment is

printenv
bootargs=mem=96M console=ttyS1,115200n8 root=/dev/mtdblock0 rw rootwait
bootdelay=3
baudrate=115200
bootfile="uImage"
flashuboot=tftp 0xc0700000 mityomap/u-boot-ubl.bin; sf probe 0; sf erase 0x10000 0x80000; sf write 0xc0700000 0x10000 ${filesize}
flashkernel=tftp 0xc0700000 mityomap/uImage; sf probe 0; sf erase 0x100000 0x280000; sf write 0xc0700000 0x100000 ${filesize}
flashubl=tftp 0xc0700000 mityomap/UBL_SPI_MEM.ais; sf probe 0; sf erase 0 0x10000; sf write 0xc0700000 0 0x10000
flashrootfs=tftp 0xc2000000 mityomap/mityomap-base-mityomapl138.jffs2; nand erase 0 0x08000000; nand write.jffs2 0xc2000000 0 ${filesize}
autoload=no
mtdids=nand0=nand
mtdparts=mtdparts=nand:128M(rootfs),-(userfs)
bootargsbase=mem=96M console=ttyS1,115200n8
flashargs=setenv bootargs ${bootargsbase} ${mtdparts} root=/dev/mtdblock0 rw,noatime rootfstype=jffs2
Freq456MHZSet=i2c mw 0x48 0x06.1 0x14; i2c mw 0x48 0x05.1 0x-Boot
Freq654MHZSet=i2c mw 0x48 0x06.1 0x14; i2c mw 0x48 0x05.1 0xC0
progdsp=sf probe 0; sf read 0xc0700000 0x580000 0x40000; bootdsp 0xc0700000
bootcmd=run progfpga;
stdin=serial
stdout=serial
stderr=serial
ethaddr=00:50:c2:e6:76:74
ver=U-Boot 2009.11-dirty (Apr 04 2012 - 13:01:11)
filesize=16A674
fileaddr=C0780000
netmask=255.255.255.0
ipaddr=192.168.0.156
serverip=192.186.0.155
progfpga=sf probe 0; sf read 0xc0700000 0x580000 0x170000; loadfpga 0xc0700000 0x170000

Environment size: 1379/65532 bytes
U-Boot >

Any ideas on where we ar egoing wrong?

Thank you

Rex


Replies (3)

RE: Programming FPGA on power up. - Added by Michael Williamson almost 9 years ago

Not seeing anything obvious. For the load process, I believe you need to specify an image size larger than the filesize (need to doublecheck this for parallel loading, but I know is true for serial loading) as the configuration process needs a few additional clocks to finish the configuration cycle once all the data has been clocked over. That may be why your tftp load sequence is not working.

Are you running on an Industrial I/O (DevKit) baseboard?

-Mike

RE: Programming FPGA on power up. - Added by Rex Taylor almost 9 years ago

Hi

I am running MityDSP Development kit Module L138-FI-225-RC.

-Rex

RE: Programming FPGA on power up. - Added by Rex Taylor almost 9 years ago

Got it sorted now, just noticed the loadaddr was incorrect

    (1-3/3)
    Go to top
    Add picture from clipboard (Maximum size: 600 MB)