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fpga EMIFA interface: BA(1) = EMA_A(14)?

Added by Dene Olsen about 11 years ago

I notice in EMIFA_iface.vhd that the EMIFA bank address bit 1 > i_ema_ba(1) < is concatenated to the top of the incoming address bus. This looks like it might indeed be the same as the 15 bit of the address bus for SDRAM interfaces, but I'd like to know where in the documentation you found that it could always be used for this.

Thanks, Dene Olsen


Replies (3)

RE: fpga EMIFA interface: BA(1) = EMA_A(14)? - Added by Michael Williamson about 11 years ago

Hi Dene,

Actually, that concatenation puts the assignment of EMA_BA(1) to bit 0 of the address (the LSB) for a 16 bit wide data interface. We typically use little endian style vectors in our VHDL code (e.g. "15 downto 0" instead of "0 to 15").

We interface to the FPGA as asynchronous 16 bit memory (using the EMA_CLK to drive the interface logic), so the EMA_BA(1) acts as part of the address decode. See section 2.5.1 regarding the addressing scheme and in particular note figure 8 (b) of TI's OMAP-L1X Processor External Memory Interface A

-Mike

RE: fpga EMIFA interface: BA(1) = EMA_A(14)? - Added by Dene Olsen about 11 years ago

Thanks,

That section and that document were exactly what I was looking for.
You're right, of course, about the concatenation being to the LS bit;
I create my vectors the same way. I'm juggling dozens of details that
I'm researching, and I was so certain the bank address must be a high
bit, that I didn't go back and look at that statement and it's signal's
definition to be certain which end it was appended to before posting.

-- Even though the board uses the L138's "asynchronous" interface, and
based on your existing code, I'm assuming that the address, data, and
control signals are synchronous to the ema-clock, and can be registered
with it. Is this correct?

-- At the start of section 2.5 of the above referenced document it describes
"Normal Mode," and "Select Strobe Mode," with reference to the operation of
the chip selects EMA_CS[5:2]. Does the MityDSP board ever use the "Select Strobe Mode?"

Regards, Dene

RE: fpga EMIFA interface: BA(1) = EMA_A(14)? - Added by Michael Williamson about 11 years ago

The FPGA address / data / control signals are indeeded sampled and run off of the EMA_CLK, which is configured for 100 MHz operation by default.

The FPGA code supplied assumes "normal mode" for chip select space 5. You are free to implement select strobe mode on another chip select space (or throw out the FPGA VHDL code we supply and write your own). There is no reason why select strobe mode could not be implemented.

-Mike

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