EMA_WAIT usage
Added by Dene Olsen about 14 years ago
I believe our design will require use of a wait signal to the processor.
There are two such signals available, one of which is used to support the NAND FLASH.
The existing code in the top level file and the EMIFA_iface file always tri-states these
signals out of the FPGA, and there don't seem to be pull-up resistors on the board, so
this seems like it will be problematical. Do you have any suggestions? If Xilinx supports
a bus-holding mode for outputs, there might be a work-around where the signals are driven
to the active state when needed, then to the inactive state briefly, then tri-stated.
Please let me know what you think.
Regards, Dene
Replies (1)
RE: EMA_WAIT usage - Added by Michael Williamson about 14 years ago
The OMAP-L138 processor includes internal pull-up / pull-down capability on just about every peripheral pin. This was done by TI in order to reduce the need for external pull-up/down resistors on a design and to provide the capability to reduce power consumption if the peripherals aren't used. By default, the EMA_WAIT pins are pulled up internally by the processor (see the OMAP-L138 data sheet and supporting manuals for more information). The NAND uses an open drain style pull down, so multiple devices could be ganged on the EMA_WAIT(0) pin if necessary by tristating (when inactive) or pulling low (when active).
I would recommend, however, that you use EMA_WAIT(1). This pin is currently not used and was reserved for the FPGA EMIFA interface for such purposes (if required). You will need, of course, to ensure that the kernel / u-Boot configures the chip select EMIFA registers appropriately.
-Mike
