Problem programming FPGA with Linux driver
Added by Steven Hill over 11 years ago
I'm having a problem programming the FPGA using the Linux driver. I am generating a core bin file using IMPACT, and the sequence of loading the file seems to execute with no problems - the "DONE" LED goes on, and I can see with a scope that the FPGA is loaded and seems to be running properly. The problem is that echo "3" does not enumerate the cores and
cat /sys/devices/fpga_ctrl/state returns 3: PROGRAM FAIL. When I run ARM software that tries to mmap the core it fails. Any idea what could be causing this?
Replies (4)
RE: Problem programming FPGA with Linux driver - Added by Michael Williamson over 11 years ago
If you are not using our framework (the base module, specifically), then the state will report failed as it is probing the base module for valid versioning information. Are you using the base module or have you implemented your own EMIFA interface?
-Mike
RE: Problem programming FPGA with Linux driver - Added by Steven Hill over 11 years ago
I am using the Critical Link framework - the base module and the EMIFA interface are untouched.
RE: Problem programming FPGA with Linux driver - Added by Steven Hill about 11 years ago
I think I figured out the source of the problem myself. Although I didn't change anything in the module files for base and emifa, in my top module port map for the base module I had disabled the "i_irq_map" and "o_irq_output" connections. When I enabled them the enumeration worked.
RE: Problem programming FPGA with Linux driver - Added by Steven Hill about 11 years ago
I guess I spoke too soon. I am still having this problem - with working FPGA code, sometimes I can get the cores to enumerate using echo "3" and sometimes it will not work. Small changes in the code of my custom core that appear to have no relationship with the base module or emifa module will cause the loading process to give a PROGRAM FAIL response even though (according to signals on the scope) it is working fine. Wilinx shows all signals routed and all constraints met with no timing errors. The only warning that I think might have some relevance (I am a novice in VHDL coding) is the following:
Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <i_ema_clk> is placed at site <T8>. The corresponding BUFG
component <emaclk_inst> is placed at site <BUFGMUX_X2Y3>. There is only a
select set of IOBs that can use the fast path to the Clocker buffer, and they
are not being used. You may want to analyze why this problem exists and
correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE
constraint was applied on COMP.PIN <i_ema_clk.PAD> allowing your design to
continue. This constraint disables all clock placer rules related to the
specified COMP.PIN. The use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition
be corrected in the design.
Any assistance would be welcome...
