Looking for help about SPI core communicate with DSPFPGAspi
Added by lijun yang almost 10 years ago
Hello,All
I have followed the instruction posted by Michael Williamson. The spi core on FPGA
--https://support.criticallink.com/redmine/boards/12/topics/1672?r=2036#message-2036
I built the FIFO using the IP CORES and put the SPI core component into the "the entity of the MityDSP_L138_top"
I am confused about some ports define
/* o_irq => irq_map(CORE_SPI_IRQ_LEVEL)(CORE_SPI_IRQ_VECTOR),
i_ilevel => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_LEVEL,2),
i_ivector => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_VECTOR,4),*/
I defined the CORE_SPI_IRQ_LEVEL,CORE_SPI_IRQ_VECTOR,CORE_SPI as
/*constant CORE_SPI_IRQ_LEVEL : integer := 0; constant CORE_SPI_IRQ_VECTOR : integer := 1; constant CORE_SPI: integer := 1;*/
Actually, it can pass the compiler.
My purpose is to use the DSPFPGASpi to test the Spi core whether it can work.
Unfortunately,I can't get the test signal from the spi.
Looking for someone know about how to using spi core communicate with DSPFPGAspi.
Thanks
Replies (3)
RE: Looking for help about SPI core communicate with DSPFPGAspi - Added by Gregory Gluszek almost 10 years ago
Hello,
constant CORE_SPI_IRQ_LEVEL : integer := 0;
Will route the IRQ to the ARM and not the DSP.
Try
constant CORE_SPI_IRQ_LEVEL : integer := 1;
Also, what base address are your feeding into the tcDspFpgaSpi constructor? Since you specified
constant CORE_SPI: integer := 1;
the base address should be 0x66000080.
Hope this helps.
Let us know if you're still having trouble.
Thanks,
\Greg
RE: Looking for help about SPI core communicate with DSPFPGAspi - Added by lijun yang almost 10 years ago
Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the VHDL code for gpio setup
/----------------------------------------------------------------------------/
--Gpio setup--
----------------------------------------------------
constant CORE_GPIO_MODULE : integer :=4; -- For Gpio core use defined in core_ids.h
constant CORE_GPIO_IRQ_LEVEL : integer :=1;-- level 1 is used for cores managed by the DSP
constant CORE_GPIO_IRQ_VECTOR :* integer :=0*;
------------------------------------------------------------------
--Gpio component define---
-------------------------------------------
gpio1 : gpio
generic map (
NUM_BANKS => 1,
NUM_IO_PER_BANK => 16
)
Port Map (
clk => ema_clk,
i_ABus => addr_r,
i_DBus => edi_r,
* o_DBus => edo_arm(CORE_GPIO_MODULE),
i_wr_en => wr_r,
i_rd_en => rd_r,
i_cs => arm_cs5_r(CORE_GPIO_MODULE),
o_irq => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR),
i_ilevel => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2),
i_ivector => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4),*
i_io => x"0000",
t_io => open,
o_io => o_diode,
i_initdir => x"FFFF",
i_initoutval => x"0000"
);
------------------------------------------------------
--------------------------------------------
The DSP code
------
-----------------------------------------------
MityDSP::tcDspFpgaGpio* mpGpio;
mpGpio = new tcDspFpgaGpio((void)0x66000080*); /* write the address*/
mpGpio->ConfigurePin(0,0,true,0,true,false); /* config the pin*/
while(1)
{
mpGpio->WritePins(0,1,0x0);
for(int i=0;i<1000;i++); /*for delay*/
mpGpio->WritePins(0,1,0x3);
}
------------------------------------------
I just want to the gpio output the value 0x0 and 0x3
Who could help me check out whether I defined these variables right or not?
Thank you very much
RE: Looking for help about SPI core communicate with DSPFPGAspi - Added by Gregory Gluszek almost 10 years ago
Hello,
Your CORE_GPIO_MODULE and base address (0x66000080) do not match one another. The address should be the CORE offset times 0x80 bytes + 0x66000000.
So
mpGpio = new tcDspFpgaGpio((void)0x66000080*); /* write the address*/
should be
mpGpio = new tcDspFpgaGpio((void)0x66000200*); /* write the address*/
since CORE_GPIO_MODULE is set to 4.
Please let us know if this fixes the problem and if you have any further issues.
Thanks,
\Greg
