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Profile

Gregory Gluszek

  • Login: ggluszek
  • Organization: Critical Link LLC
  • Registered on: 11/16/2010
  • Last connection: 07/22/2024

Issues

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Assigned issues 0 0 0
Reported issues 0 0 0

Projects

Project Roles Registered on
Mity CPU Platforms Developer 12/03/2010
Industrial I/O Board Developer 03/15/2011
Analog Expansion Board Developer 10/30/2012
MityDSP (TI TMS320C6xxx Based Products) Developer 12/03/2010
MityDSP-PRO Development Kit Developer 02/21/2013
MityDSP-L138 (ARM9 Based Platforms) Developer 12/03/2010
MitySBC-Agilex5 Developer 02/02/2024
MitySOM-335x (ARM Cortex-A8 Based Products) Developer 10/26/2011
AM335X Development Kit Developer 02/28/2012
MitySOM-335x Maker Transition Kit Developer 12/15/2016
MitySOM-5CSX Altera Cyclone V Developer 06/07/2013
MitySOM-5CSX Baseboard Developer 06/07/2013
MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Developer 07/25/2017
MitySOM-A10S Altera Arria 10 Developer 05/06/2018
MitySOM-A5 Developer 06/14/2024
MitySOM-AM57X Developer 01/27/2020
MitySOM-AM62 & MitySOM-AM62A Developer 11/01/2022
MitySOM-C10L Developer 04/04/2022
MitySOM-iMX6 Developer 04/11/2017
MityCAM Vision Cameras Developer 12/03/2010
GenTL Software Reporter 06/26/2018
MityCCD Scientific Cameras Developer 12/03/2010
Redmine Usage Developer 02/21/2012

Activity

07/23/2024

04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp... Gregory Gluszek

07/15/2024

06:58 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory... Gregory Gluszek

07/08/2024

01:20 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS
This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the o... Gregory Gluszek
01:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code
Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what erro...
Gregory Gluszek

06/05/2024

09:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r...
Gregory Gluszek

02/07/2024

04:23 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code
Hello Kyungguk Bok,
From the FPGA perspective the base_module component handles the EMIF transactions and convert...
Gregory Gluszek

03/15/2020

10:23 PM MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Support: RE: Intel OpenVINO with the VDK
Hi Ed,
I understand that Tensorflow Lite being CPU only in this instance seems like it is a deal breaker for you....
Gregory Gluszek

03/11/2020

10:02 PM MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Support: RE: Intel OpenVINO with the VDK
Hi Ed,
Regarding an Arria10 "VDK"or equivalent, the MityCAM-C50000 is an evaluation platform for the CMV50000 CMO...
Gregory Gluszek

06/24/2019

04:38 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the ...
Gregory Gluszek

08/14/2018

02:59 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM & DSP cores, undefined behaviour
My guess is that the system is running out of DSPLink buffers. I would recommend checking return codes for functions ... Gregory Gluszek

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