Critical Link Support

07/25/2024

07:47 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is reques... Gregory Gluszek

07/23/2024

04:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp... Gregory Gluszek

07/15/2024

06:58 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory... Gregory Gluszek

07/08/2024

01:20 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to access gpio using c code in yocto linux, which is created using PIO IP with HPS

This seems to be a duplicate of https://support.criticallink.com/redmine/boards/45/topics/6705. Please refer to the o... Gregory Gluszek

01:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: how to access gpio using pio ip core in c code

Hello,
Can you share capture of your console so we can evaluate what commands you are using and exactly what erro... Gregory Gluszek

06/05/2024

09:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code r... Gregory Gluszek

02/07/2024

04:23 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

Hello Kyungguk Bok,
From the FPGA perspective the base_module component handles the EMIF transactions and convert... Gregory Gluszek

03/15/2020

10:23 PM MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Support: RE: Intel OpenVINO with the VDK

Hi Ed,
I understand that Tensorflow Lite being CPU only in this instance seems like it is a deal breaker for you.... Gregory Gluszek

03/11/2020

10:02 PM MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON Support: RE: Intel OpenVINO with the VDK

Hi Ed,
Regarding an Arria10 "VDK"or equivalent, the MityCAM-C50000 is an evaluation platform for the CMV50000 CMO... Gregory Gluszek

06/24/2019

04:38 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)

Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the ... Gregory Gluszek