uPP receive clock lower limitation in SDR (Single Data Rate mode)
Added by Vivek Ponnani over 1 year ago
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
we have done following steps till date.
-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.
-- I have successfully run the example programs.
-- I have build new kernel with Analog Expansion support. We followed https://support.criticallink.com/redmine/projects/90-000173/wiki for the build of new kernel.
-- We have developed application in which DSP gets modulated data from ADC via FPGA interface. All the process is done in DSP and we are able to get demodulated output.
In this process FPGA reads data at 40MHz from ADC and sends data to uPP at 50 Mhz clock rate. everything is working fine.
Now some process is done in FPGA. FPGA sets clock to uPP interface in receive mode. Can FPGA sets the clock below 4.69 MHz for uPP(in receive mode)?
As per uPP datasheet, it limits lower clock limit in receive mode in DDR mode, The same thing applies to SDR mode? As it says "In receive mode, a channel I/O clock is generated by an external source, but the same speed limit applies", is for DDR only or SDR also?
Below is the reference point from uPP datasheet.
*2.1.3 Double Data Rate
The uPP peripheral supports two I/O clocking schemes. The first, single data rate (SDR), clocks data from
the DATA pins on either the rising edge or the falling edge (depending on UPICR.CLKINVn) of the I/O
The second clocking scheme is double data rate (DDR). In this mode, data is clocked on both the rising
and falling edges of the I/O clock. However, DDR mode imposes a lower I/O clock speed limit of one
eighth (1/8) the device CPU clock for both transmit and receive modes. The operating speed for transmit
mode with various divisors in each data rate are summarized in Table 1 (in this table, a data word is
defined as the data represented on the DATA pins; uPP supports data words in the 8-bit to 16-bit range).
In receive mode, a channel I/O clock is generated by an external source, but the same speed limit applies. *
RE: uPP receive clock lower limitation in SDR (Single Data Rate mode) - Added by Gregory Gluszek over 1 year ago
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the rate cannot be set below 4.69 MHz. However, this also seems to be assuming a default CPU clock of 300 MHz. This all seems to be tied to UPICR.CLKDIV and the maximum difference this allows between the clock fed to the uPP from the main CPU clock domain and the uPP receive clock coming in from the FPGA. It's possible, though not recommended (see below for what might be a better solution), that if you take a closer look at the rest of the clock tree you could further divide down the CPU clock being fed into the uPP to get the results you want.
That being said, rather than trying to change the clock tree and dealing with the myriad number of side effects that might have, could you add another clock domain and DCFIFO to your FPGA design? The uPP receive interface has an ENABLE pin and does not need a new sample of data each clock cycle. Therefore, why not have the logic receiving/processing your data run at the clock rate you need that is lower than 4.69 MHz, then have a DCFIFO that transitions this data to a faster clock domain that the uPP can handle (i.e. 75 MHz, 37.50 MHz, 4.69 MHz) and then have the logic in the uPP clock domain use the ENABLE signal to only mark valid data when it is in the FIFO?
Hope this helps.
Let me know if you have any further questions.
RE: uPP receive clock lower limitation in SDR (Single Data Rate mode) - Added by Vivek Ponnani about 1 year ago
Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are using reference from AnalogExpansionSuite (from Critical Link).
Initially as I mentioned, we are able to get demodulated output when FPGA reads data at 40 MHz from ADC and sends data to uPP at 50 MHz clock rate.
We have tried with 12.5 MHz (from FPGA to uPP receive of DSP) clock with some preprocessing is done in FPGA, but the data we received on DSP side is different from the data sent by FPGA. FPGA side simulation shows the data is generated correctly but when we print the debug data on DSP side, the data is different.. Now what could be the reason? Is it clock related or something else? As we have never tried uPP receive clock below 50 MHz.