Analog Expansion Board


The Industrial IO Analog Expansion Board provides both low-speed and high speed digital-to-analog (DAC) and analog-to-digital (ADC) conversion to the Industrial IO development board for integration and development using the MityDSP-L138F based family of System on Modules (SoM). The Analog Expansion Board is compatible with the MityDSP-L138F family of SoM with either the LX16 or the LX45 FPGA. Note that the current implementation provides examples of both ARM based DAC/ADC access and DSP based DAC/ADC access, so the OMAP-L138 (DSP and ARM core) based modules are required for the provided examples.

The Analog Expansion Board includes:
  • 16-bit low-speed quad channel low-speed DAC
  • 14-bit dual channel high-speed (275MSPS) DAC (unfiltered)
  • 16 channel low speed (1.8K – 23.7K SPS) ADC
  • 16 bit single channel high-speed (40MSPS) ADC (Optional ADS5562 available for 80MSPS, please contact Critical Link for details)
  • Access to 7 GPIO pins and SDA/SCL pins with standard logic levels and high-current gains.

Reference Design Files

Critical Link has the schematic and PCB design files in Altium Designer format available for this expansion board free of charge to all customers.

You can obtain these files from this link:

Getting Started with the Analog Expansion Board

In order to use the test software provided with the analog expansion board, the Kernel must be rebuilt to support the new devices on the analog expansion board.

Building the kernel with Analog Expansion Support

NOTE: If you are unfamiliar with the process of building a kernel from source, please read the Linux Kernel Guide before moving forward with this tutorial.

This guide will assume that the Linux kernel source is in ~/projects/linux-davinci and that you have already configured the environment for cross compilation.

Ther are two options for adding the Analog Expansion board to your kernel.

Option 1:

  • Use the premade defconfig file for the analog IO board. Warning: This will overwrite your current kernel config.
    make ARCH=arm CROSS_COMPILE=arm-angrstom-linux-gnueabi- industrialio_analogexp_defconfig

Option 2:

  • Open the Kernel Configuration menu.
    make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi- menuconfig
  • Navigate through the menu to the following location:
    System Type -> TI DaVinci Implementations -> Select Industrial I/O Expansion Board (Analog Expansion I/O)
    NOTE: If the option does not exist, be sure that your baseboard selection in the Select baseboard( XXXX ) menu is set to be Critical Link Industrial I/O Baseboard.
  • In the menu, select Analog Expansion I/O.
  • Save the configuration and exit menuconfig.
  • Build the kernel
    make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi- uImage
  • Build the modules
    make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi- modules
  • Install the modules to a local directory
    make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi- modules_install INSTALL_MOD_PATH=$PWD/kernel_modules

    The modules will be installed into a folder located in the current directory called kernel_modules.
  • Rebuild the FPGA kernel modules
    When installing the modules be sure to pick a local directory similar to the previous step, I.E. INSTALL_MOD_PATH=$PWD/fpga_kernel_modules.
  • Transfer the new kernel image and modules to the devkit according to where the filesystem is currently installed to (NAND, MMC, NFS...).

Preparing the devkit to use the example applications

To use the example applications, the modules built in previous steps must be inserted into the kernel. It will be assumed that the kernel modules were installed into the default location used by Linux. The path may vary according to the kernel version. To find your specific kernel version, use the command uname -a.

insmod /lib/modules/3.2.0+/extra/dsplinkk.ko
insmod /lib/modules/3.2.0+/extra/fpga_ctrl.ko
insmod /lib/modules/3.2.0+/extra/fpga_spi.ko

With the successful insertion of these modules you will see similar output as below.

root@mityomapl138:~# insmod /lib/modules/3.2.0+/extra/dsplinkk.ko
DSPLINK Module ( created on Date: Jan 13 2014 Time: 16:10:29
root@mityomapl138:~# insmod /lib/modules/3.2.0+/extra/fpga_ctrl.ko
Disabling lock debugging due to kernel taint
fpga fpga_ctrl: loading the fpga_ctrl module.
root@mityomapl138:~# insmod /lib/modules/3.2.0+/extra/fpga_spi.ko

The fpga_spi.ko module will not give any output.

Once the fpga_ctrl.ko module has been inserted the FPGA will need to be programmed. You can use the script from the latest MDK to accomplish this. A further guide on using the FPGA is located here:

The FPGA Image you will need to use these example is attached to this page. A version for both the LX16 and LX45 Spartan 6 devices are attached.

root@mityomapl138:~# ./ IndustrialIO_top_aexp_lx16.bin
fpga fpga_ctrl: Found Device ID 00-Base Module (01.01) at C681A000
fpga fpga_ctrl: Found Device ID 04-GPIO (01.03) at C681A080
fpga fpga_ctrl: Found Device ID 14-SPI Interface (02.01) at C681A100
fpga_spi 2: spi_probe() entered
fpga_spi 2: FIFO DEPTH = 64
fpga fpga_ctrl: enable_irq_vector (0,2,1)
fpga_spi 2: FPGA SPI Loaded
fpga fpga_ctrl: Found Device ID 255-Unknown (01.00) at C681A180

The board is now configured to run the example applications.

Building the provided example applications

Please refer to the following guides for all software building needs:

Linux Starter Guide

DSP Quick Start

Building FPGA Examples from MDK

Using the provided example applications

These are the usage guides for the example applications provided by Critical Link.


The on-board DAC8554 interface provides 16-Bit, quad-channel, ultra-low glitch, low power consumption, and a flexible serial host interface. Inputs are generated from OMAP processor IO pins and outputs are provided by four 2-pin connectors (J6/J10/J11/J12) on the board.

Data is sent to the DAC through a SPI device, spidev1.3. Data is sent to the DAC on the 24th falling edge of the SPI clock signal. The first 8 bits are register data while the remaining 16 bits are channel data. The TM is attached to specify the use of the register bits to select specific channels.

Example software is provided with DAC8554.c. Usage is:
  • $./DAC8554 <DAC#> <VOLTAGE>
  • VOLTAGE is a float in the range of [0,5.02]
  • DAC# represents a channel [1,4] (1->J6)(2->J10)(3->J11)(4->J12).
    • Pin 1 positive, Pin 2 ground.
The digital value of the voltage is calculated using the following formula:
  • D = (Vout x 65536) / 2.048


The on-board DAC5672 interface provides 14-bit, dual-channel, high-speed (275MSPS) digital-to-analog conversions. Inputs are generated from FPGA pins and outputs provided by two coaxial connectors (J7/J8) on the board.

Data is sent to the DAC through DSPupp.

Example software is provided with DAC5672.cpp and ARM_DAC5673.cpp. Usage is:
  • $./DAC5672<DAC5672.out> <AMPLITUDE>
  • AMPLITUDE is a float scale of a full resolution sine wave (0,1]
    • No value assume AMPLITUDE = 1
  • DAC5672.out is the filename of the DSPAPP
  • 500 KHZ sign wave is generating continuously until stopped by user input
  • NOTE: the outputs of this device are unfiltered. Locations on the board have been provided for the manual population of filter components. Output 1's locations are R85, R81, C34, and C35. Output 2's locations are R92, R112, C62, and C79.


The on-board ADS1158 interface provides a 16-channel, low noise, channel scan rates from 1.8k to 23.7k SPS per channel, a flexible input multiplexer to accept combinations of eight differential or 16 single-ended inputs, and a flexible serial host interface. Inputs are provided through four 8-pin connectors (J13/J14/J15/J16) and output is provided over SPI.

Configuration and register data is given/received over SPI using spidev3.0. The interface is configured to continuously send 2 bytes of data representing a read request and parsing 3 bytes of data back. The first byte of received data represents what channel the data represents and if it is new or not. The remaining bytes represent the channel data.

Example software is provided with ADS1158.c. Usage is:
  • $./ADS1158 <CH#>
  • CH# is in the range of [1.16]
    • [(1-4)->J16], [(5-8)->J15], [(9-12)->J14],[(13-16)->J13]
    • Even pins of connectors are tied to AGND
    • Sample output:
      root@mityomapl138:~# ./ADS1158 1
      spi mode: 0
      bits per word: 8
      max speed: 1000000 Hz (1000 KHz)
      the voltage of channel 1 is 4.03

TM is attached.


The on-board ADS5560 interface provides a 16-bit resolution, up to 40 MSPS, low noise, internal reference, and flexible features such as output interface (LVDS/CMOS) and fine gain. Input is provided through 1 coaxial connector(J9) and output is provided through FPGA IO. Note that the ADS5562 is pin-compatible with the ADS5560 and can be installed upon request for 80MSPS capabilities.

Configuration/reset of the ADC is made possible through a SPI interface, spidev1.4. The TM is provided for reference of various configurations. Data is captured using DSPupp. Before data capture, the ADS5560 must be turned on by writing a '1' to the register 0x66000202. When not using the ADC, write a '0' to the same register.

Example software is provided with ADS5560.cpp and ARM_ADS5560.cpp. Usage is:
  • $./ADS5560 <ADS5560.out>
  • ADS5560.out is the filename of the DSPAPP
  • Results are saved in the same directory as results.dat
    • The results.dat file will contain a list of 244000 samples, each sample on a separate line.

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