fpgautil read Issue
Added by pari subramaniam over 10 years ago
I'm using MityDSP-L138 Board. I have implemented a Custom IP in the FPGA board.
I'm using the CS5 ARM Chipselect and using the frame work available in fpga/vhdl directory.
Also, i'm using the fpgautil program in examples dir to read my register space in the custom IP.
When I read the register in the custom IP using fpgautil , it returns the value of the previous read. When i read the register again, it returns the actual value of register during the second read.
I checked the FPGA code and it seems to be behaving correctly.
Any idea where the issue could be?
Replies (2)
RE: fpgautil read Issue - Added by Michael Williamson over 10 years ago
Can you post (or email me) you VHDL source related to the loopback register?
Do you have Chipscope? It might be worth using chipscope to track the address / register data through the transfer cycle.
-Mike
RE: fpgautil read Issue - Added by pari subramaniam over 10 years ago
Hi Mike,
I found the issue. I was updating the edo_out signals only when rd was going high.
From the waveform i found rd signal going high after edo_out is driven on the interface.It really make sense when updated register value comes on the second register read. because the value only gets updated on rd after driving the edo_out.
Now, i removed the rd qualifier and it works fine.
Thanks Mike, the remainder about the waveform helped to relook my design.
--
Pari
