372 MHz
Added by Rob Gillis over 12 years ago
Hello,
I am running my L138 CPU at 372 MHz, which results in the EMIFA bus running at 93MHz instead of 100 MHZ.
I reused Critical Link supplied VHDL code for the EMIFA bus core. Are there any changes needed in this core to accommodate the changed bus speed? FYI, my FPGA code is running fine so far but didn't know if I might be close to the edge timing-wise.
Thanks,
Rob Gillis
Replies (1)
RE: 372 MHz - Added by Michael Williamson over 12 years ago
Hi Rob,
In general, running at different EMIFA bus rates should be OK as long as you keep in mind the following points:
1) In general, it is best to configure your new frequency before loading your FPGA. If the FPGA is using a DCM on the CLKOUT pin from the OMAP and you update the operating point (OPP) and change the clock frequency, it's likely the DCM will break lock. You can add reset logic to force the DCM to reset and resume, but you may get glitch-like behavior on your internal logic while that stuff is going on.
2) Our default constraints (in the UCF) assumes 100 MHz clock rate, so running at 93 MHz should not require modification of them. However, if you were to run faster than 100 you would need to update the constraints accordingly (and we have done this on some jobs here -- the EMIFA is spec'd to run a bit faster than 100 MHZ). The OFFSET IN pad to clock requirements may need modification in this scenario as well.
Our core logic drivers (if you are using any of it) should be smart enough program any divisors (e.g., the UART driver BAUD rate) based on the actual EMIFA clock speed.
Hope this helps.
-Mike
