FPGA clock
Added by Scott Whitney over 13 years ago
Are there any dedicated pins on the FPGA for a clock input? In the IndustrialIO.bin designs do you just use the 100 MHz EMIFA clock as the FPGA input clock? Thanks, Scott
Replies (1)
RE: FPGA clock - Added by Michael Williamson over 13 years ago
On the module itself, the EMA_CLK clock (B7) of the OMAP-L138 is connected to the FPGA. We generally use this clock for most of the core framework we provide. Given the EMIFA must run on this domain, it's convenient and allows us to avoid clock crossing logic for large portions of a typical design. Unfortunately, this clock will change if you update the processor frequency (e.g., change from 300 to 456 MHz, etc). So if you use a DCM with this clock you'll need to include an active reset circuit, or you should refrain from configuring the FPGA until after you have configured your CPU operating frequency. There are solutions/work-arounds to this issue and so far most of our customers have not had major problems with this as long as they were aware of it during their system design phase.
There are several other clock sources from the OMAP-L138 that are routed to the FPGA, including:
CLKOUT (T18), VP_CLKOUT2 (K3), VP_CLKOUT3 (K4), UPP_CH0_CLK (G1), UPP_CH1_CLK (U17), and the LCD MCLK and PCLK. These of course are geared towards interfacing the respective peripheral (video port, LCD controller, UPP port, etc.) to the FPGA. The connections should be seen in the UCF file in the MDK / Board Support Package. Not all of these clock outputs were routed to FPGA GCLK pins, but most were and those that were not should be slow enough to preclude any major timing closure issues on the Spartan 6.
In addition, several GCLK pins have been routed to the edge connector in order to allow end-users to bring in their own clock sources for external logic/timing, etc.
-Mike
