Added by Rob Gillis over 9 years ago
Following your recent BSP changes, I have modified our BSP to support the 375 MHZ L138 board.
It appears that I cannot actually get 375 MHz, but 372 is achievable using prediv=2, mult=31, and postdiv=1. Is this correct?
I assumed that the FPGA cannot run faster than 100 MHz, so I set plldiv3=4, which is 93 MHz. Is this also correct?
I made corresponding UART speed mods, do any other peripherals need to change? We using I2C1, and it is running Ok so far on new BSP.
I reused Critical Link VHDL code for the EMIFA bus core. If I'm running at 93MHz instead of 100MHz previously, are there any VHDL code changes that need to be made or will everything be Ok as is? (let me know if I should post this last question to FPGA forum instead...)
RE: 375 MHz - Added by John Pruitt over 9 years ago
I checked on the numbers and my chart consistently shows numbers 1 less than yours but I think the chart is for the actual register values and you are showing the user values. So yes, your numbers for 372 and the plldiv3 values seem correct.
I2C1 appears to run off the AUXCLK which is 24 MHZ (CLKIN) regardless of what the PLL values are so it should not need modification. Most other peripherals will probably need modifications to reflect their new clock values.
Please post the last question to the FPGA forum.
RE: 375 MHz - Added by Rob Gillis over 9 years ago
You're right, I was referring to user values, not register values. I have it running at this point, but I2C1 is affected by the CPU clock change, I think it is I2C0 connected to AUXCLK.
Does the BSP automatically handle the SPI Flash at the new speed, or will this also need to change?