Clock on MitySOM-C10G
Added by Thomas Catalino 1 day ago
I am new to FPGA in general so forgive me if this question is simple.
- Which pin/pins are configured in the hardware to be used as an input reference clock? Conceptually, how can I bring a clock signal to these pins if there is not already a clock running on them already?
Replies (1)
RE: Clock on MitySOM-C10G - Added by Noah Zins 1 day ago
On the MitySOM C10G, there is an onboard 100 MHz oscillator connected to FPGA Ball Y15, which has optional function CLKUSR. This can be used for your FPGA designs clock input, as is done in our reference design with the CLK_100 signal. Note that the X3_ENB signal (on FPGA Ball AH2) must be driven LOW to enable this clock, as is done in our reference design. Note that X3_ENB is an active low signal, contrary to Note 1 in the datasheet.
For configuring other clocks:
In the MitySOM C10G Datasheet, Table 3 lists the pins and their Optional Functions. Pins with Optional Function names that start with "CLK_2" are input clock capable pins that must be used when sending an external clock into the FPGA. There are also dedicated reference clock input (REFCLK) pins for each of the transceivers banks, listed at the bottom of Table 4.
