Activity
From 09/22/2010 to 10/21/2010
10/19/2010
- DV 08:52 PM Software Development: RE: LCD/Display questions
- We are looking at the user space solution. My hardware person says I'm wrong, he has attached the device I need to access to spi1.
- MW 08:22 PM Software Development: RE: LCD/Display questions
- On the current industrial I/O kernel configuration, SPI0 is disabled as pins associated with it are used for the MII interface. I assume you are using a custom host board solution.
Do you need access via ARM? or DSP?
If by ARM, y... - DV 08:02 PM Software Development: RE: LCD/Display questions
- I need to access spi0. It appears something related to it is compiled into the kernel (devices-da8xx.c/.o). But I don't see a mechanism on the running platform to load/access the device.
10/16/2010
- WF 07:31 PM Software Development: RE: LCD/Display questions
- Great. Sounds like for our purposes we probably don't need these commands, since we're connecting the LCD through the FPGA. We'll follow up further if that turns out not to be the case.
- MW 10:49 AM Software Development: RE: LCD/Display questions
- The "TFP410":http://focus.ti.com/docs/prod/folders/print/tfp410.html DVI interface chip is located at address 0x38 on the i2c bus. The link provided at TI allows access to the data sheet for the part, which contains a full address map f...
10/15/2010
- DV 09:25 PM Software Development: RE: LCD/Display questions
- In the wiki entry on setting up the LCD, the i2cset command was used to set a couple addresses in chip 0x38. Did that only apply to the DVI and not the LCD? If it applies to the LCD, is there documentation on what those addresses on the ...
- DV 02:47 PM Software Development: RE: Boot failure
- That worked. We are up and running.
A little search of the kernel source tree shows that in arch/arm/configs most of the "defconfig" files have CONFIG_CMDLINE set to a string that includes "rootfstype=jffs2", but the mityomapl138_defcon... - MW 01:52 PM Software Development: RE: Boot failure
- Hi Dennis,
It looks like the bootargs environment variable in u-Boot has become corrupted.
At the u-Boot prompt, try running: - DV 01:39 PM Software Development: RE: Boot failure
- Script started on Fri 15 Oct 2010 10:26:41 AM PDT
cianna@ubuntudv:~$ kermit
C-Kermit 8.0.211, 10 Apr 2004, for Linux
Copyright (C) 1985, 2004,
Trustees of Columbia University in the City of New York.
Type ? or HELP for help.
(/h... - MW 07:35 AM Software Development: RE: Boot failure
- Hi Dennis,
Please send me (or post) a dump of your terminal with the following:
# Stop in u-Boot and do a "printenv"
# Boot and allow to run until the mount error is displayed
This will help us determine the cause of the boot p...
10/14/2010
- I've inherited a board that got bricked. I'm having boot problems. The kernel loads, but gets an error: it can't mount the root file system. It's tried ext3..., and just about everything else except jffs2. I've reinstalled the kernel fro...
- WF 03:30 PM Software Development: RE: LCD/Display questions
- Thanks. This is the first of the steps we needed to understand.
I don't think we'll need help with the hardware itself; we have a guy here who's designing and building it, and as long as we can make the da8xx structures and 138 tables... - MW 03:06 PM Software Development: RE: LCD/Display questions
- Hi all,
If you have designed your own hardware using a new LCD, I'm afraid you're going to be on your own to get it functioning (unless you can provide schematics, your FPGA code, and some hardware for us to support you with). I can,... - WF 02:49 PM Software Development: RE: LCD/Display questions
- We're in need of some information on this item because our primary assignment now is to implement our LCD functionality in the unit. When can we expect to receive feedback on this issue? Thanks.
10/12/2010
- WF 07:08 PM Software Development: RE: LCD/Display questions
- Related Notes: just so you know, we have an FPGA binary which supports our new LCD panel, and it maps the memory for the LCD to the same location that's used for the current two Critical Link supported devices. So we'll be using our own ...
- DV 06:39 PM Software Development: RE: LCD/Display questions
- The wiki lists vga_640x480 and Sharp_LQ035Q7DH06 as Displays that are known. The new version of the board we have been given has a
COM57H5M06XRC (TFT-LCD) attached. What should I set for "LCD Panel" in the UBoot?
10/01/2010
- JM 11:00 AM FPGA Development: RE: TLK100 Ethernet
- Mike,
FYI It was the bias resistor. There was a type in the BOM and a 49.9K was installed instead of a 4.99K. Once I replaced this everything worked fine.
John
09/27/2010
- JM 04:24 PM FPGA Development: RE: TLK100 Ethernet
- Mike
Just to be sure can you tell me how you pinned out the PCB footprint. Does it match this picture looking from the top or component side of the board?
John - JM 03:57 PM FPGA Development: RE: TLK100 Ethernet
Mike,
After talking this out with our software guy we are convinced its as your said,one of two things. The connection form the TLK100 to the Ethernet or a configuration pullup that configured it wrong on power up. The board does...- MW 03:49 PM FPGA Development: RE: TLK100 Ethernet
- Power up the unit in your board. Stop at u_boot and type:
- JM 02:05 PM FPGA Development: RE: TLK100 Ethernet
- The JTAG R's and connector are not installed.
I have the ethernet connected to my home switch.
I set the Ip address to a fixed value the was not used on my network, that is where the 172.15.1.37 came from. It is not that on... - MW 01:55 PM FPGA Development: RE: TLK100 Ethernet
- Hi John,
It looks like the OMAP MII interface is not making it to your network. The 169.254.X.X network means that the OMAP tried to use DHCP to get a network address, but was unable to find a DHCP server and get a response. After a... - JM 01:12 PM FPGA Development: RE: TLK100 Ethernet
- Here is the ip addrs when plugged into the Critial Link and IT WORKS
Critical Link dev IT WORKS
root@mityomapl138:~# ip addr show
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
link/loopback 00:00:00:00:00:00 brd 00:00:00:... - JM 12:26 PM FPGA Development: RE: TLK100 Ethernet
- I didn't write them down I just typed them when he told me to. This was in u-boot. Once I typed them in I could ping in uboot I didn't get it to work yet in our control board but if I plug it into your development it works fine.
- MW 07:31 AM FPGA Development: RE: TLK100 Ethernet
- What were the software commands? If they involved setting the peripheral configuration in u-Boot, then they only need to be run once (assuming a "config save" was performed).
I guess I'm not sure I understand what you did to fix the ...
09/26/2010
- JM 11:13 PM FPGA Development: RE: TLK100 Ethernet
- Does the Ethernet on the MityDSP need to be initialized for each new TLK100 it gets plugged into? This one was initialized when plugged into one of the Critial Link boards and never reinitialized. When I first plugged it into the Cr...
09/25/2010
- MW 02:27 PM Software Development: RE: Clean Shutdown
- I think the most important thing is to mount the root filesystem and any filesystem you have your executable on with the noatime option, and then remount it as read only after the processor has booted. Ideally, the startup scripts from ...
09/24/2010
- JM 08:34 PM FPGA Development: RE: TLK100 Ethernet
- hey would it be possible that we talk on the phone?
858-254-0008
- MW 08:20 PM FPGA Development: RE: TLK100 Ethernet
- That message is OK. You can set up ethernet to use MII or RMII (but not both, and you're using MII).
It looks like it found the phy via MDIO OK and it is trying to get a dhcp address and failing.
You might try: - JM 08:06 PM FPGA Development: RE: TLK100 Ethernet
- I saw this among the test
EMAC: MII PHY configured, RMII PHY will not be functional
I attached the whole text - MW 07:50 PM FPGA Development: RE: TLK100 Ethernet
- Can you dump out the text from the boot sequence? Does the u-Boot locate the PHY (via the MDIO scan)?
-Mike
- JM 07:42 PM FPGA Development: RE: TLK100 Ethernet
- OK I made all the changes and it still does not work. I now think there are only two difference between out circuits:
1) pull up resistor values mine 4.75K and yours 2.2K
2) I grounded the Ethernet connector shield/cover and you ... - How do you recommend we handle shutdown of our embedded device in order to ensure the consistency of the Linux file system and anything else needed for a clean reboot?
We're doing a device that can be plugged in and unplugged at will.... - WF 12:02 PM Software Development: RE: LCD/Display questions
- We were able to get the LCD going with no problem, BTW. We'll be using it for our demo next week.
Thanks for the help.
09/23/2010
- MW 04:35 PM FPGA Development: RE: TLK100 Ethernet
- yes. you should add a pull-up.
- JM 04:16 PM FPGA Development: RE: TLK100 Ethernet
- Mike,
The green on the component means I used a different value cap or resistor. C216 is there but I used a 1uF ceramic Cap instead of the 0.1uF. I must have saw that in the TLK100 spec otherwise I would not have made it different. ... - MW 03:46 PM FPGA Development: RE: TLK100 Ethernet
- Hi John,
I think you need to tie the RESET line on the phy to the MII_RESET_N signal. The SYS_RESET_N does not get asserted in u-Boot (or the baseline kernel, as neither the SPI or audio device support has been tested and released ye... - JM 03:23 PM FPGA Development: RE: TLK100 Ethernet
- More information for you.
Attached is a comparison between the Critical link schematics and ours schematics. View this in a PDF reader and choose under menu View>Page display>Two Up to see full schematics.
The green shows the diff... - I know this is outside of your support area but I thought I would ask this in case you might have an idea of what to change or check. I appreciate any feedback your hardware guys can give me.
I used the same circuit for the Ethernet ...
09/22/2010
- MW 02:28 PM Software Development: RE: LCD/Display questions
- You'll need a different FPGA image. You also need to load an additional module (for the touchscreen controller on the LCD).
-Mike - WF 02:26 PM Software Development: RE: LCD/Display questions
- Yup. That did it.
For some reason, I had copied the instructions for the Rev. C board instead of the ones above.
Test gradient looks fine now, and so does my logo.
Now we move on to installing the LCD panel (the one we got from ... - MW 02:05 PM Software Development: RE: LCD/Display questions
- Ah. OK. You punched in the i2c commands for the Rev C board. You have 0x3f programmed into position 0x08.
Please use the following two commands (as described in the wiki): - TI 01:53 PM Software Development: RE: LCD/Display questions
- I added a simple test pattern generator to the wiki [[LCD_configuration]]. It draws a white box around the border of the frame buffer and fills it
with 16 bars. Each bar is one bit of color, so you should get 5 blue bars, 6 green bars,... - WF 01:50 PM Software Development: RE: LCD/Display questions
- Done. Here's what I see:
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 4c 01 10 04 00 00 14 64 3f 06 80 00 a9 db 97 22 L???..?d???.???"
10: 00 00 00 00 00 22 e1 5f ac b2 5c 48 41 00 00 00 ....."?_... - MW 08:17 AM Software Development: RE: LCD/Display questions
- After you are up and running, could you please run a