Activity
From 04/11/2012 to 05/10/2012
05/09/2012
- EB 04:22 PM Software Development: RE: Starterware EMIFA to FPGA example code
- Hi Mike,
In the case of 32 bit transfers as described above -
Can you tell me which 16-bit value is transferred first?
I need to make VHDL to pass all 32 bits on the same clock edge to other 32-bit IP in my FPGA design.
In other...
05/08/2012
- MW 04:55 PM FPGA Development: RE: Programming the FPGA
- Appreciate the feedback on the wiki page. I've updated it per your comments.
-Mike
- TE 04:40 PM FPGA Development: RE: Programming the FPGA
- Thanks! That worked. An even better solution than the bootfpga solution.
I was basing what I did on the wiki page for Programming the FPGA (http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA). ... - MW 03:03 PM FPGA Development: RE: Programming the FPGA
- Hi Tim / Emmett,
Did you remember to saveenv? (just checking)
A couple of things:
You might want to avoid using the "bootfpga" environment variable. We've had a couple of customers manage to brick their system by programming v... - TE 02:15 PM FPGA Development: RE: Programming the FPGA
- Emmett and I were able to get the DONE LED by calling loadfpga after the loadb 0xc0700000. The problem is that when we setup the bootfpga environment variable, it doesn't work.
I am calling the following:
loadb 0xc0700000 ->this ini... - I have read both forum entries of the same name.
The first one seems to be most applicable, since I have the MityARM-1808F with the LX16 FPGA.
I followed the instructions from the first post, which was difficult in iMPACT.
The trick...
05/02/2012
- MW 07:46 AM Software Development: RE: uPP/DMA registers
- We have demonstrated capturing as high as 100 MB/sec using UPP in 180 MB blocks without issue. So it's feasible. If you are using the LCDC controller, make sure it gets the highest bus master priority (and use some fifo'ing in your FPG...
- SM 03:10 AM Software Development: RE: uPP/DMA registers
- @Mike
Thanks for the detailed answer. We are only using the AM1808 as an embedded video server for the stream coming from the FPGA, so I cannot comment on the AM1808's H.264 decoding capabilities. But we have used the AM1808 to stream...
04/30/2012
- SW 10:12 AM Software Development: RE: uPP/DMA registers
- Shahzad, I have not found uPP drivers for the ARM in linux. My suggestion in developing them is to read the TI uPP manual, get it working in loopback mode and them transition that to you application. Be sure you set the pin mux for th...
04/29/2012
- MW 06:25 PM Software Development: RE: TI C6EZAccel library with MityDSP Platform - OmapL138
- Hi Michele,
If you would like to use the full TI DVSDK (including C6EZAccel), you can install it from TI (along with the Code Sourcery tool chain). You can use TI's libraries and filesystems, etc. The only thing you will need to do ... - Dear Sirs,
does anybody there managed to install and use the C6EZAccel library for the OMAPL138 processor, using the MityDSPL138F carrier board?
It's said to be a library that can abstract Signal Processing libraries of the C647 DSP ...
04/28/2012
- MW 10:19 AM Software Development: RE: uPP/DMA registers
- If you are not using the on-Board NAND in your design (e.g., booting to a RAMDISK or off of MMC or something), then the EMIFA would probably work. Though, you may still have to roll up a kernel module/driver to fetch the data (I would r...
- SM 09:52 AM Software Development: RE: uPP/DMA registers
- Hi Mike,
Thanks for the prompt reply. Actually the data stream is from an H.264 encoder in an FPGA, so im not sure if VPIF would be helpful here. Thats why I was looking for a uPP driver. The other option seems to be the EMIFA interfa... - MW 08:18 AM Software Development: RE: uPP/DMA registers
- Hello Shahzad,
Unfortunately, there is still no UPP driver available. Have you looked at pushing the data in using the VPIF? Supposedly, there has been some work done by TI to push a couple of different modes of camera data using th... - SM 04:11 AM Software Development: RE: uPP/DMA registers
- Hi Mike,
I am looking for a uPP driver for linux and I was searching around when I came across this thread. I know im replying to a very old thread, but I noticed that you mentioned that critical link does not have a uPP driver yet. F...
04/26/2012
- KF 12:21 AM Software Development: RE: FS Corruption due to dropping power
- Hi Mike,
Thanks for the reply. This is reasuring that it is a FS corruption problem. I have instigated a read only file system, based on your notes, and its seems to work, as in everything is mounted read only, and the application st...
04/25/2012
- MW 12:57 PM Software Development: RE: Starterware EMIFA to FPGA example code
- Hi Emmett,
Are you using linux or starterware? On starterware, if you are launching from u-Boot (which configures the EMIFA to have some nominal timings for CS5 space), then all you need to do is perform memory read or writes to 0x66... - Hello,
I have used your "EMIFA_iface" VHDL example to make a simple FPGA to test by reading/writing to registers routed to the expansion I/O on the base board.
I need example C code to make the EMIFA transfers.
In the Starterware, I...
04/13/2012
- MW 06:31 PM PCB Development: RE: RTC Battery Drain
- Hi,
Wanted to follow up on this. We have seen RTC battery drainage, but at the time we looked at it we were using Revision A silicon OMAP-L138 parts, which had some errata about power leakage that was fixed in the Revision B (standar... - MW 06:28 PM Software Development: RE: FS Corruption due to dropping power
- Hi Keith,
I have seen these symptoms before, and I'm pretty sure it's filesystem corruption related (I suspect udev related, not installing the /dev/ttyS* files due to a corrupted cached tarball of /dev which is by default stored off ...
04/12/2012
- Hi, We are developing a system where the user is unlikely to power down gracefully, even if asked to do so and ultimately intend to use a read only file system. However in testing we have not done this and have been dropping power to swi...