Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

05/15/2013

11:40 AM Software Development: RE: Video output blinks frequently

Mike,
I'm using VPIF. It *might* also be the case that my interfering tasks are interfering because they're trans... Helmut Forren

11:10 AM Software Development: RE: Video output blinks frequently

VPIF! Helmut Forren

11:08 AM Software Development: RE: Video output blinks frequently

Mike:
Thanks for the advice. FYI, this is same project as Wade Calcutt is working on, regarding FPGA loading prop... Helmut Forren

10:26 AM Software Development: RE: Video output blinks frequently

I suspect that you need to increase the bus master DMA priority of the VPIF or LCDC peripherals (it's not clear to me... Michael Williamson

10:24 AM Software Development: RE: Video output blinks frequently

Helmut,
First thing is which version of the kernel are you running?
__uname -a__
Also the command __nice__ c... Jonathan Cormier

10:10 AM Software Development: Video output blinks frequently

My custom system is based on the MityOMAP-L138F.
At random times, but fairly frequently, my video output corrupts ... Helmut Forren

05/14/2013

10:43 AM FPGA Development: RE: FPGA load verification

You might bring the DCM status lines (particularly the lock status) to a scope just to see if that is the core issue.... Michael Williamson

05/13/2013

03:12 PM FPGA Development: RE: FPGA load verification

Mike,
To my knowledge we're not changing the CPU frequency. That being said, one of the output messages during Lin... Wade Calcutt

01:09 PM FPGA Development: RE: FPGA load verification

Wade,
The EMIFA output clock can change if the OMAP-L138 CPU frequencies are modified (the EMIFA output clock is o... Michael Williamson

12:28 PM FPGA Development: RE: FPGA load verification

Hi Mike,
Thanks for your response and troubleshooting suggestions.
To answer your questions:
*Are you using ... Wade Calcutt

12:12 PM FPGA Development: RE: FPGA load verification

Hi Wade,
If you are getting the "done" light on the part, then the FPGA is loading correctly and it's 99.999999999... Michael Williamson

11:33 AM FPGA Development: FPGA load verification

I'm using a MityDSP-L138F with an FPGA load that is a modified version of the example code provided in the Vision Dev... Wade Calcutt

05/09/2013

03:48 PM Software Development: RE: GPIO interrupt in MityOMAP-L138F

I am glad you were able to figure this out, and these notes are helpful. Thanks for posting them.
We have been st... Michael Williamson

02:58 PM Software Development: RE: GPIO interrupt in MityOMAP-L138F

Hi Mike,
I successfully implemented an interrupt example using FPGA Gpio core and your core libraries on DSP.
Mayb... Michele Canepa

05/07/2013

07:08 AM Software Development: RE: ethernet over USB don't work

If you want to force HOST mode, then you will need to rebuild the kernel and change the call from:
mityomapl138_us... Michael Williamson

06:29 AM Software Development: RE: Problem with uPP in DLB

Hi François,
I am a newbie, and trying to create Upp Loopback with MityDSP1810F board.
Can you give your Upp Loopb... minh tung

05/06/2013

09:59 PM Software Development: RE: ethernet over USB don't work

Sorry for late reply. Thanks for your help at first.
I have removed the RNDIS driver.
What I use is a USB2.0 ethe... yilin wang

09:59 PM Software Development: RE: ethernet over USB don't work

Sorry for late reply. Thanks for your help at first.
I have removed the RNDIS driver.
What I use is a USB2.0 ethe... yilin wang

05/04/2013

09:24 AM Software Development: RE: ethernet over USB don't work

I think you are using the wrong approach to do this. The RNDIS driver (g_ether.ko) is to allow IP over USB and is a ... David Rice

05/03/2013

10:59 PM Software Development: ethernet over USB don't work

Hi,
I'm using MityARM-1808 with my own carrier board.
It has a hi-speed USB 2.0 to ethernet controller(smsc7500) co... yilin wang

05/02/2013

09:55 AM FPGA Development: RE: Verilog codes for MityDSP-L138F

You can use verilog, the Xilinx tools support it. However, all of our refernece code is in VHDL.
It may be possib... Michael Williamson

09:48 AM FPGA Development: Verilog codes for MityDSP-L138F

Hello,
I am a beginner with FPGA programming and MityDSP-L138F. I know the board currently uses VHDL. Can I write ... Quoc Lai

04/30/2013

07:30 AM FPGA Development: RE: OFFSET constraint never passes timing

Did not receive it. Michael Williamson

04/29/2013

05:17 PM FPGA Development: RE: OFFSET constraint never passes timing

I tried:
-shreg_extract = checked
-shreg_min_size = 5
No difference.
There is a DCM on i_ema_clk already.
Shou... Emmett Bradford

04:28 PM FPGA Development: RE: OFFSET constraint never passes timing

If you have it disabled, then it won't happen. Try leaving it enabled and seeting min size to 5.
The other thing ... Michael Williamson

11:55 AM FPGA Development: RE: OFFSET constraint never passes timing

Thanks Mike,
In Synthesis Properties, HDL Options, I have:
-shreg_extract = unchecked
-shreg_min_size = 3
I see... Emmett Bradford

10:46 AM FPGA Development: RE: OFFSET constraint never passes timing

Sorry about the -3 vs -2 issue. We will correct that on our next release. However, several designs have been valida... Michael Williamson

09:56 AM FPGA Development: RE: OFFSET constraint never passes timing

The paths that are failing are from the pads to the EMIF module, I don't have any code connecting there.
Also, the... Emmett Bradford

04/23/2013

01:55 PM FPGA Development: RE: OFFSET constraint never passes timing

Hi,
Two things.
1) You don't need the OFFSET=OUT spec with our IP. It turns out there is an extra clock in the... Michael Williamson

01:38 PM Software Development: RE: SATA mount point

You can also run "udevadm monitor" to watch for udev activity.
Tim Iskander

01:29 PM Software Development: RE: SATA mount point

Scott,
I'm not sure whats going on. I can't explain why one would work as expected and the other doesn't. Its po... Jonathan Cormier

11:44 AM Software Development: RE: SATA mount point

the mmc card does not affect the mounting. It behaves the same way with or without it. I don't know if there are an... Scott Whitney

11:39 AM Software Development: RE: SATA mount point

Just as a curiousity, have you tried to see if adding/removing the mmc card affects how the sata drive mounts. Its t... Jonathan Cormier

11:35 AM Software Development: RE: SATA mount point

i am uploading 4 files both my /etc/fstab and the output of fdisk. This is from 2 different systems with different S... Scott Whitney

11:24 AM Software Development: RE: SATA mount point

Scott,
Could you attach your fstab for both machines as well as the output of 'fdisk -l'?
-Jonathan Jonathan Cormier

11:07 AM Software Development: SATA mount point

_Hello,
I've got a few mityDSP developement kits and am attaching SATA SSD drives to them. They are formated EXT4 w... Scott Whitney

04/22/2013

02:11 PM FPGA Development: OFFSET constraint never passes timing

I am using the following timing constraints.
If I remember correctly, I started from the industrial I/O example and ... Emmett Bradford

04/17/2013

06:31 PM Software Development: RE: USB on the go speed

Hi Mike,
It would be great if I can get a copy of your sample code! It would help tremendously if I can get close to... Lars Majlof

05:03 PM Software Development: RE: USB on the go speed

Hi Lars,
We have found that RNDIS has been very slow as well and we have not used the serial gadget, but I would s... Michael Williamson

04:20 PM Software Development: USB on the go speed

Hi,
When I configure Linux (3.2.0+) to use the ethernet gadget with RNDIS support, I get poor data transfer speeds. ... Lars Majlof