Activity
From 07/05/2024 to 08/03/2024
07/29/2024
- 05:36 PM PCB Development: RE: X1 component SiLabs 590 BA100M000G depopped
- See "PCN20220621000":https://support.criticallink.com/redmine/attachments/download/31707/PCN20220621000.pdf linked fr...
- Hello,
we are working on transferring our design from the Spartan 6 build to the A7 SOM and an engineer noticed n...
07/24/2024
- 02:31 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- I figure it's about 10% of the CPU when operating 1200 baud and 1 response per second; it gets much lower as you appr...
07/22/2024
- 07:21 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- > before shutting off the 485 driver
Any idea how often the shutting down occurs? - 07:19 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- I patched the 8250.c file to increase the 10ms timeout. I found the timeout is really there only to assure the uart t...
07/19/2024
- 06:14 PM PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies
- Dan,
That clears things up perfectly. Thank you for a quick and comprehensive response. - 06:10 PM PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies
- Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector.... - All,
I am designing a carrier board for the MityDSP-L138F with A7 FPGA. I have noticed some inconsistencies with the...
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