Daniel Vincelette

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Project	Roles	Registered on
Mity CPU Platforms	Developer	09/28/2011
Industrial I/O Board	Developer	09/28/2011
Analog Expansion Board	Developer	10/30/2012
MityDSP (TI TMS320C6xxx Based Products)	Developer	09/28/2011
MityDSP-PRO Development Kit	Developer	02/21/2013
MityDSP-L138 (ARM9 Based Platforms)	Developer	09/28/2011
MitySBC-Agilex5	Developer	01/19/2024
MitySOM-335x (ARM Cortex-A8 Based Products)	Developer	10/26/2011
AM335X Development Kit	Developer	02/28/2012
MitySOM-335x Maker Transition Kit	Developer	12/15/2016
MitySOM-5CSX Altera Cyclone V	Developer	06/07/2013
MitySOM-5CSX Baseboard	Developer	06/07/2013
MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON	Developer	07/25/2017
MitySOM-A10S Altera Arria 10	Manager, Developer	05/06/2018
MitySOM-A5	Developer	06/14/2024
MitySOM-AM57X	Manager, Developer	01/27/2020
MitySOM-AM62 & MitySOM-AM62A	Manager, Developer	11/01/2022
MitySOM-C10L	Developer	04/04/2022
MitySOM-iMX6	Developer	04/11/2017
MityCAM Vision Cameras	Developer	09/28/2011
GenTL Software	Reporter	06/26/2018
MityCCD Scientific Cameras	Developer	09/28/2011
Redmine Usage	Developer	02/21/2012

06:10 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138F Block Diagram Inconsistencies: Hi Dylan,
The external input to the Boot Config Block is the EXT_BOOT# signal pin bin 12 of the SO-DIMM connector.... Daniel Vincelette
02:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hello,
For the reference project the makefile removes those lines from the sdc file before it does the build, if y... Daniel Vincelette

07:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hello,
I have verified that the reference design does meet timing when built via the makefile (ie make rbf). The m... Daniel Vincelette

01:39 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: It sounds like you are on edge for timing so please verify that your design meets timing via TimeQuest in Quartus. Al... Daniel Vincelette

01:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hello,
For the case that you are seeing 60% packet lose, what did you change in the reference FPGA project that wa... Daniel Vincelette

06:18 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM: Hello,
You shouldn't need to update the compiler or path from the default that are filled out by the bsp-editor. D... Daniel Vincelette

01:34 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM: Hello,
The Altera Cyclone V SoC boot process involves several steps to initialize and start up the system. The Cyc... Daniel Vincelette

06:48 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Get URL from jenkins file: Hello,
I believe the Jenkins file you are referring to was provided as a reference and contains internal links to ... Daniel Vincelette

02:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access: Hello,
If you want to intergate the data inside the FPGA instead of having the HPS involved you could look into us... Daniel Vincelette

08:39 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Error in u-boot. cyclone v 5CSEBA4U2317 SOM: Hello,
From the error it looks like the SPL isn't able to correctly read the MBR/Partition table on the SD card. T... Daniel Vincelette

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