Activity
From 07/29/2016 to 08/27/2016
08/24/2016
- 09:59 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
I'll cleanup and push the project today. I'll also go through and write down what needs to be updated in...
08/23/2016
- 03:52 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
So I'm still not getting any output on my monitors. However, I tried adjusting the monitor settings and I... - 02:18 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Sorry about that, it's attached now
- 01:41 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Can you post that image for me to try?
- 01:34 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Awesome, I'll glad it did work on the TV!
I was able to recreate what I think you're seeing on your monitor. If I ... - 12:32 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Awesome, thanks.
I tried a large screen Samsung HDTV and your latest build works.
I'm hoping that the HDTV's ar... - 12:10 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Good catch, I'm doing a build now with the those back porch values. I'll let you know when it's finished.
- 12:00 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- One thing of note, based on the original qsys file from the wiki page, it seems the back porch values are not the sam...
- 11:51 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- No luck, same result, just a black screen.
- 11:14 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
Attached is a new image. The only thing I changed was that I updated the output delays for the data/cont...
08/22/2016
- 02:10 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- That's ok, thanks for the update Dan. Feel free to post an updated image anytime, even if you don't have a ton of te...
- 02:07 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Steve,
I'm terribly sorry for the radio silence. Unfortunately I've been travelling for the past week so I haven't... - 07:43 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
Any update on this? Have you been able to review the scope shots?
Best,
Steve
08/17/2016
- 10:35 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
See attached. The index.txt file in the zip package describes each scope shot. Let me know what other me...
08/16/2016
- 03:35 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
Sure thing, I can take these shots first thing in the morning and get them back to you.
Steve - 01:12 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
Hmm good point that it you've already vetted the monitor you're using. Seeing as you're getting the disp... - 07:39 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
Thanks for the detail on the I2C fix.
I've tested on two monitors. On one of them, I am certain it sup... - 03:05 PM Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Jonathan/Dan,
Solved.... Yes, that was the difference in the two kernels, ipv6 was being built as a module in the ...
08/15/2016
- 04:12 PM Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Hi Brian,
I've updated the wiki for building the kernel and have added steps for building the modules, it can be f... - 03:20 PM Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Both udp6/tcp6 and '::' points to an error with ipv6 support. Looking at your .config file shows ipv6 being built as...
- 03:05 PM Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Jonathan,
So I built a new kernel setting the base configuration as mitysom5csx_devkit_defconfig without doing the... - 03:11 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Steve,
Sorry for the delay, I was travelling Friday afternoon.
To fix for the I2C issue was that I resample... - 10:45 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan,
This image doesn't show anything on my monitor. Upon first booting it, right after the console printed "S...
08/12/2016
- 03:27 PM Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- I have both the L2_3Y8 and H4_3YA.. Attached is the config file for my 3YA. Dont think it really matters. Both error ...
- 02:25 PM Software Development: RE: Network Communication MitySOM Custom Kernel Configuration
- Can you post your .config file?
Thanks
Jonathan Cormier - Hello,
I have a MitySOM dev board with the 5CSE-H4-3YA. I am able to use the pre-built binary SD card image for ne... - 12:15 PM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hi Dan
Thanks for this. I can try the image on Monday and report back results.
Can you provide a little detail... - 11:56 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hello Steve,
I've created an alpha SD card image that from my testing has fixed the i2c failures. The filesystem a...
08/11/2016
- 10:05 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Dan,
The network stability problem has disappeared after removing the skews. Thanks for the suggestion!
I'll...
08/10/2016
- 11:12 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Jared,
Looking at the sockit dts(https://github.com/altera-opensource/linux-socfpga/blob/socfpga-4.1.22-ltsi-rt... - 10:38 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I've been performing more testing on the Altera 4.1.22 LTSI RT branch.
Physical setup: MitySOM 5CSX ...
08/09/2016
- 10:30 AM FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boot
- Hello Steve,
There was a bit of stability issue with the I2C interface to the HDMI transmitter IC. I thought my ne... - Hello,
I'm trying to run the HDMI output image provided on the wiki. I haven't modified anything just written the... - 10:24 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Jared,
Glad to hear that worked for you! If you run into trouble getting your defconfig/dts setup how you want ... - 09:40 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
Thanks for pushing the dizzy (1.7) branch. I've successfully gotten to the same point you did in your f...
08/05/2016
- 02:05 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Jared,
Sorry for the delay.
I just pushed a dizzy(1.7) branch to our git repo: http://support.criticallink.c...
08/03/2016
- 03:27 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I proceeded to try to use Yocto to build the Altera 4.1.22 LTSI RT kernel based on your suggestions abo...
08/02/2016
- 11:55 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Jared,
That sounds like a perfect approach. For building the file system we do use yocto, which as you saw i... - 10:26 AM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I've been going through the instructions on the Wiki to get an SD card image of my creation working. I'...
07/29/2016
- 03:01 PM Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Jared,
I did a quick test here and was able to boot altera's 4.1.22 ltsi rt kernel using the MitySOM-5CSX de...
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