- Table of contents
- FPGA FAQs
- What peripherals can be routed from the HPS through the FPGA fabric?
- How do I route HPS peripherals to an FPGA pin?
- If I route an interrupt to the HPS in QSYS, which interrupt will it show up at?
- What are the preferred FPGA clocking pins?
- I opened a previous project in QSYS and an error is shown as follows:
- Error printed when programming FPGA "resource busy or time out"
What peripherals can be routed from the HPS through the FPGA fabric?¶
You can route the following HPS peripherals through the FPGA fabric:
- EMAC0 (routed as GMII, not RGMII as when used as an HPS peripheral) - http://www.altera.com/literature/hb/cyclone-v/cv_54017.pdf
- EMAC1 (routed as GMII, not RGMII as when used as an HPS peripheral) - http://www.altera.com/literature/hb/cyclone-v/cv_54017.pdf
- SPI0 Master and Slave
- SPI1 Master and Slave
You should not route these peripherals through the Fabric as they are used on the module
- UART0 (main console debug interface)
- QSPI (NOR memory)
- I2C0 (Factory EEPROM, LED controller, temp sensor and RTC)
You cannot route these peripherals through the Fabric at this time due to Altera Cyclone V restrictions:
- SDIO (MMC/SD card)
- USB1 (USB Phy support on the module)
- TRACE pins
How do I route HPS peripherals to an FPGA pin?¶
You can configure the mode of each HPS peripheral through QSys to determine whether it is routed through the HPS interface or the FPGA fabric.The following steps show how to route i2c2 through the FPGA fabric:
- Open the HPS component in qsys
- Go to the Peripheral Pin Multiplexing tab
- Set the drop down box next to I2C2 pin multiplexing to FPGA
- Click Finish
You will notice that there is now the data and clock line for i2c2 under the HPS component, export these signals so they can be used in the top level entity.
If I route an interrupt to the HPS in QSYS, which interrupt will it show up at?¶
The ARM interrupt numbers for the FPGA interrupts routed to the HPS are documented in table 9-2 of the Cortex-A9 Microprocessor Unit Subsystem document from Altera.
From the table, FPGA interrupts 0-63 map to GIC interrupt controller interrupts 72-135, respectively. These are the numbers if you are registering for IRQs directly in linux using the request_irq() linux API.
However, in the device tree, the interrupts for drivers are defined using a 3 number vector, for example:
interrupts = < 0 40 1 >;
The 3 arguments are whether the interrupt is shared or not (shared peripheral interrupt flag), and is normally always set to 0. The second number is the offset index into the interrupt controller. The 3rd number is the interrupt edge or level specifier (1 = rising, 2 = falling if supported, 4 is level high). GIC interrupt numbers are offset by 32 in the table. So for device tree the linux interrupt numbers are 32 less than the numbers listed in the table. For example, the FPGA interrupt level 0 should map to linux/ARM interrupt number 40 (72-32 = 40) in the devicetree specifier.
What are the preferred FPGA clocking pins?¶
There are 3 pairs of Differential Clock IO's available on the module edge connector:
Bank 8A - CLK7p (pin 177)
Bank 8A - CLK7n (pin 179)
Bank 4A - CLK3p (pin 99)
Bank 4A - CLK3n (pin 101)
Bank 3B - CLK1p (pin 163)
Bank 3B - CLK1n (pin 165)
I opened a previous project in QSYS and an error is shown as follows:¶
"list element in braces followed by "}" instead of space while executing "lindex $result 0" (procedure "reconfig_param_handler" line 120) invoked from within "reconfig_param_handler" (procedure "validation_callback" line 461) invoked from within "validation_callback"
To resolve this error, in most cases, go to the "File" menu of QSYS and then select "Refresh System". Press "close" once the refresh is complete and the error should be resolved.
Error printed when programming FPGA "resource busy or time out"¶
If not properly implemented the nCONFIG pin can cause the FPGA fabric to be put into a reset state. This pin has a 10K ohm pull-up resistor to 3.3V on the module. Do not use a pull-down resistor on the nCONFIG net or this will force the FPGA into the reset state.
Go to top