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HSMC Dual Camera Link

This page provides information and source code for a project that exercises the HSMC interface to produce test pattern frames in the Camera Link standard.

Requirements

You will need the following for this example:

  1. A Critical Link MityARM-5CSX module and development board.
  2. A Microtronix Datacom Ltd. Camera Link Transmitter HSMC Daughter Card.
  3. Two Camera Link cables of matched length.
  4. A device that can capture dual Camera Link data in the full extended 10 tap 8 bit configuration.
    1. This project was tested using the EPIX PIXCI® E8 frame grabber.
  5. An Altera USB-Blaster, or other device capable of debug on the Cyclone V.

Hardware Setup

  1. Connect the Microtronix Datacom Ltd. Camera Link Transmitter HSMC Daughter Card to the HSMC connector on the MityARM-5CSX development board labeled as FULL HSMC.
  2. Use the Camera Link cables to connect the HSMC daughter card to the capture device (i.e. the EPIX PIXCI® E8 frame grabber).

Building the FPGA

  1. Download and extract the attached zip file mityarm_5csx_dev_board_hsmc_10tap_8bit_camlink.zip.
  2. Open the project in Quartus II 13.1.
  3. Use the MegaWizard Plug-In Manger to re-generate the following cores:
    1. pll85
    2. pll85_phase_adjusted
    3. tx_5lane
    4. issp
  4. Open Qsys and run generate on mityarm_5csx_dev_board.qsys.
  5. Close Qsys.
  6. Press the purple 'play' button in Quartus to start compilation.

Executing the example

Note: The Critical Link MityARM-5CSX development board was not created specifically to work with the Microtronix Datacom Ltd. Camera Link Transmitter HSMC Daughter Card. Therefore, due to routing complications, the Altera In-System Sources and Probe Editor (ISSP Editor) must be used to manually adjust the phase of one of the Camera Link clocks in order to produce valid output frames.

  1. Program the FPGA with the output from compilation.
    1. This can either be accomplished by using the USB Blaster.
  2. Setup the capture device to capture a frame of size 2560 x 2160, 8 bits per pixel, 10 tap 8 bit Camera Link Full Extended configuration.
  3. Open the ISSP Editor in Quartus.
  4. Use the ISSP Editor to change source bits 2-4 to select different phases for Camera Link Chip Z clock.
  5. Once the correct phase is selected the capture device should show a vertical gradient image that changes with each new frame.

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