Writing to HPS Memory


In this example the FPGA will write a counting pattern into HPS memory through the SDRAM controller. This example has two pieces, the FPGA side and Linux side. The FPGA holds the components that write into the HPS memory. The Linux side starts the transfer.

The FPGA image is composed of 5 components:

  1. HPS - Has a 64 bit Avalon memory mapped slave port added to it for communication with the SDRAM controller. More ports can be added for read, write, and read/write (refer to the SDRAM Controller section of the HPS TRM).
  2. System ID Peripheral - Holds a unique ID for the FPGA image; this can be read from the HPS.
  3. Modular SGDMA Dispatcher - The SGDMA components allow for converting an Avalon stream to a memory mapped interface (it also handles doing the reverse). In this example the SGDMA is used for handling the transfer of the count pattern to the HPS memory. More information about the Modular SGDMA can be obtained at the Altera Forum.
  4. SGDMA Write Master - as described by the Modular SGDMA Dispatcher.
  5. Avalon Stream Count Source - a simple component that outputs a counting pattern.

The Linux side is composed of a simple application that interfaces with the SGDMA dispatcher over the HPS Lightweight bridge. The application maps in the control register and descriptor register of the SGDMA dispatcher using mmap of /dev/mem.


In order for the FPGA to have a spot in memory to write to, the memory that Linux uses needs to be limited. To do this an argument needs to be set for the kernel in uboot.

In this example we will limit Linux to use 512M of the 1G RAM. This example is assuming that the MMC will be the boot device so the updated boot argument will look like

mmcboot=setenv bootargs console=ttyS0,57600 root=${mmcroot} rw rootwait mem=512M;bootm ${loadaddr} - ${fdtaddr}

The mem=512M was the part that was added.

The FPGA will be writing around the 800M region of the HPS DDR.


Steps to use:
  1. Boot to linux
  2. Program the FPGA
  3. Run the following command to take the FPGA SDRAM port out of reset
    memtool -32 0xFFC25080=0x110
  4. Run the write2hpsmem application
  5. Use memtool to go see that the count pattern was written to the HPS memory
    memtool -32 0x30000000 32

    Here is the expected output:
    root@socfpga_cyclone5:~# memtool -32 0x30000000 32
    Reading 0x32 count starting at address 0x30000000
    0x30000000:  00000000 00000000 00000000 00000001
    0x30000010:  00000000 00000002 00000000 00000003
    0x30000020:  00000000 00000004 00000000 00000005
    0x30000030:  00000000 00000006 00000000 00000007
    0x30000040:  00000000 00000008 00000000 00000009
    0x30000050:  00000000 0000000A 00000000 0000000B
    0x30000060:  00000000 0000000C 00000000 0000000D
    0x30000070:  00000000 0000000E 00000000 0000000F
    0x30000080:  00000000 00000010 00000000 00000011
    0x30000090:  00000000 00000012 00000000 00000013
    0x300000A0:  00000000 00000014 00000000 00000015
    0x300000B0:  00000000 00000016 00000000 00000017
    0x300000C0:  00000000 00000018


Both the Quartus project, that has been built with Quartus 13.1, and the software is provided. A prebuilt FPGA image and Linux application are also provided with the source. - HPS DDR Write Exmaple (1.1 MB) Daniel Vincelette, 12/05/2013 03:32 PM

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