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A5E-Base-Example

Overview

The A5E base example is an HPS-centric reference design. The base configuration is intended as a clean starting point for HPS boot, memory bring-up, and peripheral validation.

The primary purpose of this design is to:

  • Bring up the Agilex 5 HPS
  • Connect the HPS to onboard LPDDR4 through the HPS EMIF controller
  • Expose the board's HPS-connected peripheral interfaces for software development and platform bring-up
  • Provide a small amount of FPGA-side support logic that the HPS can access through the lightweight HPS-to-FPGA bridge

In other words, this project is a clean starting point for HPS boot, Linux bring-up, peripheral validation, and incremental expansion of the design.

Base Design Structure

The diagram below shows how the HPS, its memory and the small amount of FPGA-side support logic fit together.

                       ┌──────────────────────────────┐
                       │         LPDDR4 Memory        │
                       │    via HPS EMIF Controller   │
                       └──────────────────────────────┘
                                      ▲
                                      │ HPS EMIF
                                      ▼
        ┌───────────────────────────────────────────────────────────┐
        │                        Agilex 5 HPS                       │
        │                                                           │
        │  - Boot / application processing                          │
        │  - Peripheral controllers and HPS I/O                     │
        │  - HPS GP signals                                         │
        └───────────────────────────────────────────────────────────┘
                                ▲                     ▲
                                │ HPS pins            │ Lightweight
                                │ to board I/O        │ HPS-to-FPGA
                                │                     │ bridge
                                ▼                     ▼
          ┌──────────────────────────────┐   ┌──────────────────────────────┐
          │ Board-Level HPS Interfaces   │   │ Minimal FPGA Support Logic   │
          │                              │   │                              │
          │ - SD/MMC                     │   │ - sysid                      │
          │ - USB / Ethernet / serial    │   │ - 32-bit PIO input/output    │
          │ - I2C / I3C / GPIO           │   │ - USB-C interrupt PIO        │
          │                              │   │ - reset / board glue         │
          └──────────────────────────────┘   └──────────────────────────────┘

What This Project Offers

This project is useful as a base platform because it already provides:

  • A known-good HPS + LPDDR4 hardware starting point
  • HPS peripheral pin muxing for the board-level interfaces needed for software bring-up
  • A lightweight HPS-to-FPGA control path for simple registers and board support functions
  • A minimal fabric footprint that is easy to understand and extend

HPS-Connected Peripheral Interfaces

The base design primarily exposes HPS peripheral pins rather than custom FPGA logic. In the current base configuration this includes:

  • SD/MMC interface signals, along with card-detect and media-select style GPIO support
  • USB1 ULPI signals and USB 3.1 sideband/PHY support signals
  • USB 2.0 ULPI signals (MitySOM Only)
  • EMAC1 Ethernet interface signals (MitySOM-Mini and MitySBC Only)
  • MDIO management signals for Ethernet PHY bring-up (MitySOM-Mini and MitySBC Only)
  • UART1 for serial console / software interaction
  • I2C1 for board-level peripheral access
  • Additional I2C buses on the EMAC-dedicated HPS pins (three on MitySOM, one on MitySBC)
  • I3C0 for additional peripheral connectivity
  • I3C1 for additional peripheral connectivity (MitySOM-Mini Only)
  • Miscellaneous GPIO-based board control signals such as reset, presence-detect, and enable lines

FPGA-Side Support Logic

The design still includes a few useful support blocks:

  • Sysid so software can identify the generated hardware build
  • PIO output 32-bit register space on the lightweight HPS-to-FPGA bridge
  • PIO input 32-bit register space on the lightweight HPS-to-FPGA bridge
  • USB-C interrupt PIO so the HPS can observe the external USB-C interrupt line through an IRQ-capable register
  • Fan controller driving the board fan PWM and reading its tachometer (MitySBC Only)

These blocks are intended for simple platform control/status functions rather than high-bandwidth data movement.

HPS GP / Board Bring-Up Hooks

The design also leaves a few simple HPS-to-fabric hooks in place that are useful during bring-up:

  • HPS GP output is used to release the fabric from reset
  • HPS GP outputs are used to drive debug LEDs
  • The lightweight HPS-to-FPGA bridge can be used to add more simple board-control features later without restructuring the design

Building the Example

Compile the FPGA design

Refer to Building the FPGA and Bootloader (MitySOM) or Building the FPGA and Bootloader (MitySBC) for building the FPGA design. Navigate into the mitysom-a5e[-mini]-ref-base or mitysbc-a5e-ref-base example project before compiling the design.

  • Ensure to flash the resulting a5e.hps.jic onto the hardware
  • Ensure to replace the a5e.core.rbf on the SD card

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