A5E-FPGA_EMIF-Example¶
Overview¶
The A5E FPGA EMIF example builds on the base A5E design and adds an FPGA-side LPDDR4 memory subsystem.
The HPS platform and board-level bring-up infrastructure from the base design are still present, but the primary feature of this example is the fpga_emif_subsys. This subsystem instantiates the Intel LPDDR4 EMIF IP and the support blocks needed to clock it, reset it, and present a fabric-facing memory access interface.
This example is best viewed as a subsystem integration reference design. It shows how the FPGA LPDDR4 interface is brought into the project and wired up, while leaving room for future user logic or traffic-generation logic to be added around it.
This example is provided for the MitySOM and MitySBC carriers. The MitySOM-Mini does not bring out an FPGA-side LPDDR4 interface and has no fpga-emif project. The configured memory size and clock vary by model, covering 4 GB and 8 GB parts at 800, 1066 and 1333 MHz.
FPGA EMIF Subsystem¶
The FPGA EMIF subsystem contains four main blocks:
- fpga_emif_0 - Intel LPDDR4 EMIF IP
- s0_axi4_clock_bridge_0 - provides the internal subsystem clock
- s0_axi4_reset_bridge_0 - provides the internal subsystem reset
- s0_axi4_mm_bridge_0 - bridges the fabric-side Avalon-MM interface to the EMIF AXI4 interface
User traffic should be connected on the fabric-facing s0 side of s0_axi4_mm_bridge_0.
At the top level of the design:
- The subsystem clock is driven from hps_subsys.intel_agilex_5_soc_0_h2f_user0_clk
- The subsystem reset is driven from fabric_reset_controller_0.reset_out
- The LPDDR4 pins and EMIF reference clock are exported to the FPGA-side memory interface pins
hps_subsys.intel_agilex_5_soc_0_h2f_user0_clk (100 MHz example) FPGA_CLKIN_P
│ │
▼ │ ref_clk
┌──────────────────────────┐ ▼
│ s0_axi4_clock_bridge_0 │ ┌──────────────────────────┐ LPDDR4 pins ┌───────────────┐
└──────────────────┬───────┘ │ fpga_emif_0 │◄──────────────►│ FPGA LPDDR4 │
│ │ (LPDDR4 EMIF IP) │ └───────────────┘
├─────── clock ────────► └──────────────────────────┘
│ ▲ ▲
│ │ AXI4 │
▼ │ │
Avalon-MM ┌──────────────────────────┐ │ │
Connection to user logic ◄───────────────►│ s0_axi4_mm_bridge_0 │◄────────────┘ │
│ (Avalon-MM to AXI4) │ │
└──────────────────────────┘ │
▲ │
│ reset │
│ │
┌─────────────────┴────────────────────────────────────┴┐
fabric_reset_controller_0.reset_out ►│ s0_axi4_reset_bridge_0 │
└───────────────────────────────────────────────────────┘
What This Project Offers¶
This project provides:
- A reference integration of FPGA-side LPDDR4 on the A5E platform
- A ready-made EMIF subsystem with clock, reset, and MM-to-AXI4 bridge structure already assembled
- A clear starting point for adding FPGA masters, test logic, or application logic that need external LPDDR4
- The same HPS bring-up platform as the base design, with the FPGA EMIF subsystem added alongside it
Memory Path¶
The important data path in this example is:
- Fabric-side Avalon-MM traffic enters s0_axi4_mm_bridge_0
- The bridge converts that traffic to the AXI4 interface expected by fpga_emif_0
- The EMIF IP drives the external FPGA LPDDR4 memory interface
The subsystem's fabric-side integration point is the s0 side of s0_axi4_mm_bridge_0. No master is attached to that interface in the current example.
Clocking and Reset¶
The FPGA EMIF subsystem is integrated into the rest of the design as follows:
- s0_axi4_clock_bridge_0 fans out the subsystem clock
- That clock is used by the MM bridge and by the EMIF IP control/data interfaces
- s0_axi4_reset_bridge_0 fans out the subsystem reset
- That reset is applied to the MM bridge and the EMIF IP initialization/control interfaces
- In this design, the subsystem clock bridge is fed from the user clock, which is 100 MHz in this example
- This is useful for integration and bring-up, but it will not allow full bandwidth to the FPGA LPDDR4
- If higher bandwidth is desired, connect s0_axi4_clock_bridge_0 to a faster clock source
External FPGA LPDDR4 Interface¶
The EMIF IP exports the expected FPGA-side LPDDR4 signals, including:
- LPDDR4 reference clock input
- CK / CKE / CS / CA control signals
- DQ / DQS / DMI data signals
- Memory reset
- OCT / RZQ support signal
These signals are pinned out in the generated project and connected to the FPGA-side LPDDR4 memory interface on the board.
Scope of This Example¶
This example focuses on integrating the FPGA EMIF subsystem itself.
It does not add a dedicated traffic generator, benchmark engine, or end-user memory test application around the subsystem. In the current top-level design, the subsystem is integrated, clocked, reset, and pinned out, but no example traffic source is attached to exercise the memory path.
That makes this design a good base for:
- adding custom FPGA masters
- adding a simple memory test block
- extending the design into a higher-level memory-access example later
Building the Example¶
Compile the FPGA design¶
Refer to Building the FPGA and Bootloader (MitySOM) or Building the FPGA and Bootloader (MitySBC) for building the FPGA design. Navigate into the mitysom-a5e-ref-fpga-emif or mitysbc-a5e-ref-fpga-emif example project before compiling the design.
- Ensure to flash the resulting a5e.hps.jic onto the hardware
- Ensure to replace the a5e.core.rbf on the SD card