A5E 10 Gigabit Ethernet SFP+ Example¶

Overview¶

This example demonstrates 10 Gigabit Ethernet operation over the SFP+ port on the MitySOM-A5E Mini
development kit using Intel's GTS (General Transceiver Subsystem) Ethernet IP. The design includes
Intel's reference packet_client and loopback_client modules, along with Signal Tap instances for
monitoring transmit and receive traffic at the IP boundary.

The packet client generates raw Ethernet frames and reports transmit/receive statistics through a
memory-mapped register interface accessible from the HPS via the lightweight HPS-to-FPGA bus.

Supported Hardware¶

• MitySOM-A5E Mini baseboard (all module variants)
  • A5ED-B14-1X8-MRC-B0 (default)
  • A5ED-B14-1X4-MRC-B0
  • A5ED-B06-1X2-MRI-CS
  • A5ED-B9-XXF-RC-X

This example was tested using two MitySOM-A5E Mini development kits connected back-to-back with
SFP-10G-SR transceivers and a crossover fiber cable.

Known Issues and Limitations¶

• This example uses the raw packet generation logic from Intel's reference design. It does not include
  formal Linux Ethernet drivers for standard network stack operation.
• Only one transceiver interface (SFP or USB3) may be active at a time. Enabling SFP_EXAMPLE will
  automatically disable USB3 during project generation.
• The client loopback mode has not been fully validated.

Requirements¶

• Quartus Prime Pro Edition 25.3.1
• AArch64 cross-compiler toolchain (e.g., aarch64-none-linux-gnu-gcc or aarch64-linux-gnu-gcc)
• Reference SD card with a compatible Linux filesystem
• This project is configured for HPS-first boot

Building the FPGA Design¶

Step 1 — Check your configuration (optional but recommended)¶

Before generating the project, verify that the settings look correct for your target hardware. Replace
AGILEX5_MODEL with the model number printed on your module label.

make AGILEX5_MODEL=A5ED-B14-1X8-MRC-B0 SFP_EXAMPLE=1 preview_config

SFP_EXAMPLE=1 is the default for all MitySOM-A5E Mini model strings, so it may be omitted for
convenience. Review the printed configuration. If everything looks correct, proceed to the next step.

Step 2 — Generate the project from TCL¶

make AGILEX5_MODEL=A5ED-B14-1X8-MRC-B0 generate_from_tcl

This command:

• Cleans any previously generated files
• Generates the Quartus project files (.qpf, .qsf), top-level HDL, and SDC from the TCL scripts
• Generates the Platform Designer (.qsys) system

Step 3 — Build the JIC¶

make jic

This will:

1. Run the full Quartus compile flow (synthesis, place, route, timing analysis)
2. Clone and build ARM Trusted Firmware (branch QPDS25.3_REL_GSRD_PR) if not already present
3. Clone and build U-Boot SPL (branch socfpga_v2025.07) if not already present
4. Package the resulting SOF with the U-Boot SPL into output_files/a5e.jic

Programming the Board¶

Flash the JIC into the on-board QSPI NOR flash via JTAG using the Quartus programmer. If multiple
boards are connected, jtagconfig can be used to identify cable indices.

jtagconfig --setparam 1 JtagClock 16M
quartus_pgm -c 1 -m jtag -o "ip;output_files/a5e.jic@2" 

After flashing, power-cycle the board.

Also copy the updated boot.scr to the SD card boot partition:

cp scripts/boot.scr /path/to/sdcard/boot/

Running the Test¶

Non-loopback bidirectional flow (two boards)¶

Connect two MitySOM-A5E Mini boards back-to-back via SFP+ and boot both boards into Linux.

HPS GPIO quick reference (SFP mapping)¶

The SFP control/status signals are connected to the HPS general-purpose interface bits as follows:

HPS GP bit	Direction	SFP/GTS signal	Notes
s_hps_gp_out[7]	HPS -> FPGA	SFP_TX_DIS	Transmit disable control
s_hps_gp_out[8]	HPS -> FPGA	SFP_RS0	SFP rate-select control
s_hps_gp_in[4]	FPGA -> HPS	o_tx_pll_locked	GTS TX PLL lock status
s_hps_gp_in[6]	FPGA -> HPS	o_rx_pcs_ready	GTS RX PCS ready status
s_hps_gp_in[13]	FPGA -> HPS	SFP_TX_FLT_N	Module TX fault (active low)
s_hps_gp_in[14]	FPGA -> HPS	SFP_MOD_PRSNT_N	Module present (active low)
s_hps_gp_in[15]	FPGA -> HPS	SFP_LOS	Loss-of-signal indicator
s_hps_gp_in[16]	FPGA -> HPS	s_sys_pll_locked	System PLL locked status

For the examples below, memtool 0xF8D08200 1 reads the HPS GP input register.

1. Verify the link is up

Check GTS status via the HPS general-purpose input register. Bit 6 (o_rx_pcs_ready) and bit 4
(o_tx_pll_locked) should read 1 when the link is established:

memtool 0xF8D08200 1

2. Start transmitting packets (run on both boards)

memtool 0x22000000=5

3. Stop transmitting

memtool 0x22000000=1
memtool 0x22000000=0

4. Read packet statistics

memtool 0x22000000 32

The 32-bit registers at the following offsets report packet counts:

Address	Description
0x22000010	Transmitted packets
0x22000014	Received packets
0x22000018	Received packets with errors

5. Read GTS Ethernet statistics registers

Dump the 10 GbE RX statistics counters:

memtool 0x20150000 64

Dump the 10 GbE TX statistics counters:

memtool 0x20160000 64

Register definitions are documented in the Intel 10/25 GbE GTS Statistics Counters reference.

Loopback flow (single board)¶

1. Configure the loopback board

memtool 0x20024040=0xF

2. Configure the transmit board and start sending

memtool 0x20024040=5

3. Stop transmitting

memtool 0x20024040=7

4. Read packet statistics

memtool 0x20024000 32

Address	Description
0x20024010	Transmitted packets
0x20024014	Received packets
0x20024018	Received packets with errors

Accessing Signal Tap¶

Signal Tap instances are included for monitoring transmit and receive data at the packet client
interface. After a successful compile, open the auto-generated STP file in the Quartus Signal Tap
Logic Analyzer:

./qdb/_compiler/a5e/root_partition/25.3.1/final/1/stp_gen/generated.stp