MitySOM-A5E PCIe Gen 3x4 EP Example Project¶

This page is a work in progress. When this warning is removed, the instructions should be considered finalized.

Overview¶

This example demonstrates using the Agilex 5 PCIe Hard IP in an Endpoint (EP) configuration at Gen 3 (8 GT/s) link rates with x4 data lanes. In this example, the end connector interface of the MitySOM-A5E Standard Development Kit is connected to a host PC running linux Ubuntu via a samtec PCIEC-064-0500-EC-EM-P-85 cable assembly.

The demonstration allows a host PC to perform the following tasks:

• Transfer data from a Host PC memory buffer to the HPS SDRAM memory. Data can also be viewed by the HPS processor.
• Transfer Data from the HPS SDRAM memory to a Host PC memory buffer.
• Read the contents of the SYSID module that is in the Agilex 5 FPGA fabric and shared between the Host PCIE access and the HPSFPGALW bridge.

This demonstration does not include support for SDRAM cache coherency management between the Agilex-5 ARM complex and the SDRAM memory. The Agilex-5 ARM accesses the memory using non-cache modes.

The FPGA project utilizes the Multi-Channel DMA

Supported Hardware¶

• MitySOM-A5E Standard Development Kit Baseboard (all variants)
  • A5ED-B64-188-SRC-X (default)
  • A5ED-B64-144-SRC-X
  • A5ED-B66-188-SRC-X
  • A5ED-B66-144-SRC-X

Known Issues and Limitations¶

Requirements¶

• Quartus Prime Pro Edition 25.3.1
• AArch64 cross-compiler toolchain (e.g., aarch64-none-linux-gnu-gcc or aarch64-linux-gnu-gcc)
• Reference SD card with a compatible Linux filesystem
• This project is configured for HPS-first boot
• Linux PC supporting 64-bit PCIe transfers
• Open PCIe slot with x4 lanes available
• Samtec PCIEC-064-0500-EC-EM-P-85 PCIe Slot to Edge cable extender.

Building the FPGA Design¶