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1
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/*
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* AM33XX mux data
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
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*
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* Copyright (C) 2009 Nokia
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* Copyright (C) 2009 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include "mux.h"
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#ifdef CONFIG_OMAP_MUX
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22
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#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
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24
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{ \
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.reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \
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26
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.gpio = (g), \
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27
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.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
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}
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/* AM33XX pin mux super set */
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static struct omap_mux __initdata am33xx_muxmodes[] = {
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32
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_AM33XX_MUXENTRY(GPMC_AD0, 0,
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33
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"gpmc_ad0", "mmc1_dat0", NULL, NULL,
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34
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NULL, NULL, NULL, NULL),
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35
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_AM33XX_MUXENTRY(GPMC_AD1, 0,
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36
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"gpmc_ad1", "mmc1_dat1", NULL, NULL,
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NULL, NULL, NULL, NULL),
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38
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_AM33XX_MUXENTRY(GPMC_AD2, 0,
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39
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"gpmc_ad2", "mmc1_dat2", NULL, NULL,
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40
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NULL, NULL, NULL, NULL),
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41
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_AM33XX_MUXENTRY(GPMC_AD3, 0,
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42
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"gpmc_ad3", "mmc1_dat3", NULL, NULL,
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NULL, NULL, NULL, NULL),
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_AM33XX_MUXENTRY(GPMC_AD4, 0,
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45
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"gpmc_ad4", "mmc1_dat4", NULL, NULL,
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46
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NULL, NULL, NULL, NULL),
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47
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_AM33XX_MUXENTRY(GPMC_AD5, 0,
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48
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"gpmc_ad5", "mmc1_dat5", NULL, NULL,
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49
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NULL, NULL, NULL, NULL),
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50
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_AM33XX_MUXENTRY(GPMC_AD6, 0,
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51
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"gpmc_ad6", "mmc1_dat6", NULL, NULL,
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52
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NULL, NULL, NULL, NULL),
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53
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_AM33XX_MUXENTRY(GPMC_AD7, 0,
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54
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"gpmc_ad7", "mmc1_dat7", NULL, NULL,
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55
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NULL, NULL, NULL, NULL),
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56
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_AM33XX_MUXENTRY(GPMC_AD8, 0,
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57
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"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
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58
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NULL, NULL, NULL, NULL),
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59
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_AM33XX_MUXENTRY(GPMC_AD9, 0,
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60
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"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
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61
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NULL, NULL, NULL, NULL),
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62
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_AM33XX_MUXENTRY(GPMC_AD10, 0,
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63
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"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
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64
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NULL, NULL, NULL, NULL),
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65
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_AM33XX_MUXENTRY(GPMC_AD11, 0,
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66
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"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
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67
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NULL, NULL, NULL, NULL),
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68
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_AM33XX_MUXENTRY(GPMC_AD12, 0,
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69
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"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
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70
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NULL, NULL, NULL, NULL),
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71
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_AM33XX_MUXENTRY(GPMC_AD13, 0,
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72
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"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
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73
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NULL, NULL, NULL, NULL),
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74
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_AM33XX_MUXENTRY(GPMC_AD14, 0,
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75
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"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
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76
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NULL, NULL, NULL, NULL),
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77
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_AM33XX_MUXENTRY(GPMC_AD15, 0,
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78
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"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
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79
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NULL, NULL, NULL, NULL),
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80
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_AM33XX_MUXENTRY(GPMC_A0, 0,
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81
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"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
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NULL, NULL, NULL, "gpio1_16"),
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_AM33XX_MUXENTRY(GPMC_A1, 0,
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"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
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NULL, NULL, NULL, NULL),
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86
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_AM33XX_MUXENTRY(GPMC_A2, 0,
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"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
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NULL, NULL, NULL, NULL),
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89
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_AM33XX_MUXENTRY(GPMC_A3, 0,
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90
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"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
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NULL, NULL, NULL, NULL),
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92
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_AM33XX_MUXENTRY(GPMC_A4, 0,
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"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
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"gpmc_a20", NULL, NULL, NULL),
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_AM33XX_MUXENTRY(GPMC_A5, 0,
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"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
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"gpmc_a21", NULL, NULL, "gpio1_21"),
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_AM33XX_MUXENTRY(GPMC_A6, 0,
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"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
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"gpmc_a22", NULL, NULL, "gpio1_22"),
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_AM33XX_MUXENTRY(GPMC_A7, 0,
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102
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"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
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NULL, NULL, NULL, NULL),
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_AM33XX_MUXENTRY(GPMC_A8, 0,
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"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
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NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
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_AM33XX_MUXENTRY(GPMC_A9, 0,
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108
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"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
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NULL, NULL, "mcasp0_fsx", "gpio1_25"),
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_AM33XX_MUXENTRY(GPMC_A10, 0,
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"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
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NULL, NULL, "mcasp0_axr0", "gpio1_26"),
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_AM33XX_MUXENTRY(GPMC_A11, 0,
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"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
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115
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NULL, NULL, "mcasp0_axr1", "gpio1_27"),
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116
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_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
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"gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
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118
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"mmc1_sdcd", NULL, NULL, NULL),
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119
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_AM33XX_MUXENTRY(GPMC_WPN, 0,
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120
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"gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
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121
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"mmc2_sdcd", NULL, NULL, NULL),
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122
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_AM33XX_MUXENTRY(GPMC_BEN1, 0,
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123
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"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
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NULL, NULL, "mcasp0_aclkr", NULL),
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125
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_AM33XX_MUXENTRY(GPMC_CSN0, 0,
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126
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"gpmc_csn0", NULL, NULL, NULL,
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127
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NULL, NULL, NULL, "mmc1_sdwp"),
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128
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_AM33XX_MUXENTRY(GPMC_CSN1, 0,
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129
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"gpmc_csn1", NULL, "mmc1_clk", NULL,
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NULL, NULL, NULL, "gpio1_30"),
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_AM33XX_MUXENTRY(GPMC_CSN2, 0,
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"gpmc_csn2", NULL, "mmc1_cmd", NULL,
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133
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NULL, NULL, NULL, "gpio1_31"),
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_AM33XX_MUXENTRY(GPMC_CSN3, 0,
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135
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"gpmc_csn3", NULL, NULL, "mmc2_cmd",
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NULL, NULL, NULL, NULL),
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137
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_AM33XX_MUXENTRY(GPMC_CLK, 0,
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138
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"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
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139
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NULL, NULL, "mcasp0_fsr", NULL),
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140
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_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
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"gpmc_advn_ale", NULL, NULL, NULL,
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NULL, NULL, NULL, "mmc1_sdcd"),
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143
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_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
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"gpmc_oen_ren", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL),
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146
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_AM33XX_MUXENTRY(GPMC_WEN, 0,
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"gpmc_wen", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL),
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_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
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"gpmc_ben0_cle", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL),
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_AM33XX_MUXENTRY(LCD_DATA0, 0,
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153
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"lcd_data0", "gpmc_a0", NULL, NULL,
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NULL, NULL, NULL, "gpio2_6"),
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_AM33XX_MUXENTRY(LCD_DATA1, 0,
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"lcd_data1", "gpmc_a1", NULL, NULL,
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NULL, NULL, NULL, NULL),
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158
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_AM33XX_MUXENTRY(LCD_DATA2, 0,
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159
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"lcd_data2", "gpmc_a2", NULL, NULL,
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160
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NULL, NULL, NULL, NULL),
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161
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_AM33XX_MUXENTRY(LCD_DATA3, 0,
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162
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"lcd_data3", "gpmc_a3", NULL, NULL,
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163
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NULL, NULL, NULL, NULL),
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164
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_AM33XX_MUXENTRY(LCD_DATA4, 0,
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165
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"lcd_data4", "gpmc_a4", NULL, NULL,
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166
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NULL, NULL, NULL, NULL),
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167
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_AM33XX_MUXENTRY(LCD_DATA5, 0,
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168
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"lcd_data5", "gpmc_a5", NULL, NULL,
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169
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NULL, NULL, NULL, NULL),
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170
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_AM33XX_MUXENTRY(LCD_DATA6, 0,
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171
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"lcd_data6", "gpmc_a6", NULL, NULL,
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172
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NULL, NULL, NULL, NULL),
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173
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_AM33XX_MUXENTRY(LCD_DATA7, 0,
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174
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"lcd_data7", "gpmc_a7", NULL, NULL,
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175
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NULL, NULL, NULL, NULL),
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176
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_AM33XX_MUXENTRY(LCD_DATA8, 0,
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177
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"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
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178
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NULL, NULL, "uart2_ctsn", NULL),
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179
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_AM33XX_MUXENTRY(LCD_DATA9, 0,
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180
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"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
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181
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NULL, NULL, "uart2_rtsn", NULL),
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182
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_AM33XX_MUXENTRY(LCD_DATA10, 0,
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183
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"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
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184
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NULL, NULL, NULL, NULL),
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185
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_AM33XX_MUXENTRY(LCD_DATA11, 0,
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186
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"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
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187
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"mcasp0_axr2", NULL, NULL, NULL),
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188
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_AM33XX_MUXENTRY(LCD_DATA12, 0,
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189
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"lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
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190
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"mcasp0_axr2", NULL, NULL, "gpio0_8"),
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191
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_AM33XX_MUXENTRY(LCD_DATA13, 0,
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192
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"lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
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193
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"mcasp0_axr3", NULL, NULL, NULL),
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194
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_AM33XX_MUXENTRY(LCD_DATA14, 0,
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195
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"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
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196
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NULL, NULL, NULL, NULL),
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197
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_AM33XX_MUXENTRY(LCD_DATA15, 0,
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198
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"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
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199
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"mcasp0_axr3", NULL, NULL, NULL),
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200
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_AM33XX_MUXENTRY(LCD_VSYNC, 0,
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201
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"lcd_vsync", NULL, NULL, NULL,
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202
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NULL, NULL, NULL, NULL),
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203
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_AM33XX_MUXENTRY(LCD_HSYNC, 0,
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204
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"lcd_hsync", NULL, NULL, NULL,
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205
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NULL, NULL, NULL, NULL),
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206
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_AM33XX_MUXENTRY(LCD_PCLK, 0,
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207
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"lcd_pclk", NULL, NULL, NULL,
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208
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NULL, NULL, NULL, NULL),
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209
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_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
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210
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"lcd_ac_bias_en", NULL, NULL, NULL,
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211
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NULL, NULL, NULL, "gpio2_25"),
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212
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_AM33XX_MUXENTRY(MMC0_DAT3, 0,
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213
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"mmc0_dat3", NULL, NULL, NULL,
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214
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NULL, NULL, NULL, NULL),
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215
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_AM33XX_MUXENTRY(MMC0_DAT2, 0,
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216
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"mmc0_dat2", NULL, NULL, NULL,
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217
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NULL, NULL, NULL, NULL),
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218
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_AM33XX_MUXENTRY(MMC0_DAT1, 0,
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219
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"mmc0_dat1", NULL, NULL, NULL,
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220
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NULL, NULL, NULL, NULL),
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221
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_AM33XX_MUXENTRY(MMC0_DAT0, 0,
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222
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"mmc0_dat0", NULL, NULL, NULL,
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223
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NULL, NULL, NULL, NULL),
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224
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_AM33XX_MUXENTRY(MMC0_CLK, 0,
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225
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"mmc0_clk", NULL, NULL, NULL,
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226
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NULL, NULL, NULL, NULL),
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227
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_AM33XX_MUXENTRY(MMC0_CMD, 0,
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228
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"mmc0_cmd", NULL, NULL, NULL,
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229
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NULL, NULL, NULL, NULL),
|
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230
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_AM33XX_MUXENTRY(MII1_COL, 0,
|
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231
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"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
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232
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"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
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233
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_AM33XX_MUXENTRY(MII1_CRS, 0,
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234
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"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
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235
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"mcasp1_aclkx", NULL, NULL, NULL),
|
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236
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_AM33XX_MUXENTRY(MII1_RXERR, 0,
|
|
237
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"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
|
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238
|
"mcasp1_fsx", NULL, NULL, NULL),
|
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239
|
_AM33XX_MUXENTRY(MII1_TXEN, 0,
|
|
240
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"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
|
|
241
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"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
|
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242
|
_AM33XX_MUXENTRY(MII1_RXDV, 0,
|
|
243
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"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
|
|
244
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"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),
|
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245
|
_AM33XX_MUXENTRY(MII1_TXD3, 0,
|
|
246
|
"mii1_txd3", "d_can0_tx", "rgmii1_td3", NULL,
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247
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"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
|
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248
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_AM33XX_MUXENTRY(MII1_TXD2, 0,
|
|
249
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"mii1_txd2", "d_can0_rx", "rgmii1_td2", NULL,
|
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250
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"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
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251
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_AM33XX_MUXENTRY(MII1_TXD1, 0,
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252
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"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
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253
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"mcasp1_axr1", NULL, "mmc1_cmd", NULL),
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254
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_AM33XX_MUXENTRY(MII1_TXD0, 0,
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255
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"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
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256
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"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
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257
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_AM33XX_MUXENTRY(MII1_TXCLK, 0,
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258
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"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
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259
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"mmc1_dat0", NULL, "mcasp0_aclkx", NULL),
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260
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_AM33XX_MUXENTRY(MII1_RXCLK, 0,
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261
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"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
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262
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"mmc1_dat1", NULL, "mcasp0_fsx", NULL),
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263
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_AM33XX_MUXENTRY(MII1_RXD3, 0,
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|
264
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"mii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5",
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265
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"mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"),
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266
|
_AM33XX_MUXENTRY(MII1_RXD2, 0,
|
|
267
|
"mii1_rxd2", "uart3_txd", "rgmii1_rd2", "mmc0_dat4",
|
|
268
|
"mmc1_dat3", "uart1_rin", "mcasp0_axr1", "gpio2_19"),
|
|
269
|
_AM33XX_MUXENTRY(MII1_RXD1, 0,
|
|
270
|
"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
|
|
271
|
"mcasp1_fsr", NULL, "mmc2_clk", NULL),
|
|
272
|
_AM33XX_MUXENTRY(MII1_RXD0, 0,
|
|
273
|
"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
|
|
274
|
"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),
|
|
275
|
_AM33XX_MUXENTRY(MII1_REFCLK, 0,
|
|
276
|
"rmii1_refclk", NULL, "spi1_cs0", NULL,
|
|
277
|
"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", NULL),
|
|
278
|
_AM33XX_MUXENTRY(MDIO_DATA, 0,
|
|
279
|
"mdio_data", NULL, NULL, NULL,
|
|
280
|
"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),
|
|
281
|
_AM33XX_MUXENTRY(MDIO_CLK, 0,
|
|
282
|
"mdio_clk", NULL, NULL, NULL,
|
|
283
|
"mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),
|
|
284
|
_AM33XX_MUXENTRY(SPI0_SCLK, 0,
|
|
285
|
"spi0_sclk", "uart2_rxd", NULL, NULL,
|
|
286
|
NULL, NULL, NULL, "gpio0_2"),
|
|
287
|
_AM33XX_MUXENTRY(SPI0_D0, 0,
|
|
288
|
"spi0_d0", "uart2_txd", NULL, NULL,
|
|
289
|
NULL, NULL, NULL, "gpio0_3"),
|
|
290
|
_AM33XX_MUXENTRY(SPI0_D1, 0,
|
|
291
|
"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
|
|
292
|
NULL, NULL, NULL, NULL),
|
|
293
|
_AM33XX_MUXENTRY(SPI0_CS0, 0,
|
|
294
|
"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
|
|
295
|
NULL, NULL, NULL, NULL),
|
|
296
|
_AM33XX_MUXENTRY(SPI0_CS1, 0,
|
|
297
|
"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
|
|
298
|
NULL, "mmc0_sdcd", NULL, NULL),
|
|
299
|
_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
|
|
300
|
"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
|
|
301
|
"spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
|
|
302
|
_AM33XX_MUXENTRY(UART0_CTSN, 0,
|
|
303
|
"uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda",
|
|
304
|
"spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"),
|
|
305
|
_AM33XX_MUXENTRY(UART0_RTSN, 0,
|
|
306
|
"uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl",
|
|
307
|
"spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"),
|
|
308
|
_AM33XX_MUXENTRY(UART0_RXD, 0,
|
|
309
|
"uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,
|
|
310
|
NULL, NULL, NULL, NULL),
|
|
311
|
_AM33XX_MUXENTRY(UART0_TXD, 0,
|
|
312
|
"uart0_txd", "spi1_cs1", "d_can0_rx", NULL,
|
|
313
|
NULL, NULL, NULL, NULL),
|
|
314
|
_AM33XX_MUXENTRY(UART1_CTSN, 0,
|
|
315
|
"uart1_ctsn", NULL, NULL, "i2c2_sda",
|
|
316
|
"spi1_cs0", NULL, NULL, NULL),
|
|
317
|
_AM33XX_MUXENTRY(UART1_RTSN, 0,
|
|
318
|
"uart1_rtsn", NULL, NULL, "i2c2_scl",
|
|
319
|
"spi1_cs1", NULL, NULL, NULL),
|
|
320
|
_AM33XX_MUXENTRY(UART1_RXD, 0,
|
|
321
|
"uart1_rxd", "mmc1_sdwp", "d_can1_tx", NULL,
|
|
322
|
NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"),
|
|
323
|
_AM33XX_MUXENTRY(UART1_TXD, 0,
|
|
324
|
"uart1_txd", "mmc2_sdwp", "d_can1_rx", NULL,
|
|
325
|
NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"),
|
|
326
|
_AM33XX_MUXENTRY(I2C0_SDA, 0,
|
|
327
|
"i2c0_sda", NULL, NULL, NULL,
|
|
328
|
NULL, NULL, NULL, NULL),
|
|
329
|
_AM33XX_MUXENTRY(I2C0_SCL, 0,
|
|
330
|
"i2c0_scl", NULL, NULL, NULL,
|
|
331
|
NULL, NULL, NULL, NULL),
|
|
332
|
_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
|
|
333
|
"mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk",
|
|
334
|
"mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"),
|
|
335
|
_AM33XX_MUXENTRY(MCASP0_FSX, 0,
|
|
336
|
"mcasp0_fsx", NULL, NULL, "spi1_d0",
|
|
337
|
"mmc1_sdcd", NULL, NULL, NULL),
|
|
338
|
_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
|
|
339
|
"mcasp0_axr0", NULL, NULL, "spi1_d1",
|
|
340
|
"mmc2_sdcd", NULL, NULL, NULL),
|
|
341
|
_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
|
|
342
|
"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
|
|
343
|
NULL, NULL, NULL, "gpio3_17"),
|
|
344
|
_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
|
|
345
|
"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
|
|
346
|
"mmc0_sdwp", NULL, NULL, NULL),
|
|
347
|
_AM33XX_MUXENTRY(MCASP0_FSR, 0,
|
|
348
|
"mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
|
|
349
|
NULL, "pr1_pru0_pru_r30_5", NULL, NULL),
|
|
350
|
_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
|
|
351
|
"mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
|
|
352
|
NULL, NULL, NULL, NULL),
|
|
353
|
_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
|
|
354
|
"mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",
|
|
355
|
NULL, NULL, NULL, "gpio3_21"),
|
|
356
|
_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
|
|
357
|
"xdma_event_intr0", NULL, NULL, NULL,
|
|
358
|
"spi1_cs1", NULL, NULL, NULL),
|
|
359
|
_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
|
|
360
|
"xdma_event_intr1", NULL, NULL, "clkout2",
|
|
361
|
NULL, NULL, NULL, NULL),
|
|
362
|
_AM33XX_MUXENTRY(WARMRSTN, 0,
|
|
363
|
NULL, NULL, NULL, NULL,
|
|
364
|
NULL, NULL, NULL, NULL),
|
|
365
|
_AM33XX_MUXENTRY(PWRONRSTN, 0,
|
|
366
|
NULL, NULL, NULL, NULL,
|
|
367
|
NULL, NULL, NULL, NULL),
|
|
368
|
_AM33XX_MUXENTRY(NMIN, 0,
|
|
369
|
NULL, NULL, NULL, NULL,
|
|
370
|
NULL, NULL, NULL, NULL),
|
|
371
|
_AM33XX_MUXENTRY(XTALIN, 0,
|
|
372
|
NULL, NULL, NULL, NULL,
|
|
373
|
NULL, NULL, NULL, NULL),
|
|
374
|
_AM33XX_MUXENTRY(XTALOUT, 0,
|
|
375
|
NULL, NULL, NULL, NULL,
|
|
376
|
NULL, NULL, NULL, NULL),
|
|
377
|
_AM33XX_MUXENTRY(TMS, 0,
|
|
378
|
NULL, NULL, NULL, NULL,
|
|
379
|
NULL, NULL, NULL, NULL),
|
|
380
|
_AM33XX_MUXENTRY(TDI, 0,
|
|
381
|
NULL, NULL, NULL, NULL,
|
|
382
|
NULL, NULL, NULL, NULL),
|
|
383
|
_AM33XX_MUXENTRY(TDO, 0,
|
|
384
|
NULL, NULL, NULL, NULL,
|
|
385
|
NULL, NULL, NULL, NULL),
|
|
386
|
_AM33XX_MUXENTRY(TCK, 0,
|
|
387
|
NULL, NULL, NULL, NULL,
|
|
388
|
NULL, NULL, NULL, NULL),
|
|
389
|
_AM33XX_MUXENTRY(TRSTN, 0,
|
|
390
|
NULL, NULL, NULL, NULL,
|
|
391
|
NULL, NULL, NULL, NULL),
|
|
392
|
_AM33XX_MUXENTRY(EMU0, 0,
|
|
393
|
NULL, NULL, NULL, NULL,
|
|
394
|
NULL, NULL, NULL, NULL),
|
|
395
|
_AM33XX_MUXENTRY(EMU1, 0,
|
|
396
|
NULL, NULL, NULL, NULL,
|
|
397
|
NULL, NULL, NULL, NULL),
|
|
398
|
_AM33XX_MUXENTRY(RTC_XTALIN, 0,
|
|
399
|
NULL, NULL, NULL, NULL,
|
|
400
|
NULL, NULL, NULL, NULL),
|
|
401
|
_AM33XX_MUXENTRY(RTC_XTALOUT, 0,
|
|
402
|
NULL, NULL, NULL, NULL,
|
|
403
|
NULL, NULL, NULL, NULL),
|
|
404
|
_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
|
|
405
|
NULL, NULL, NULL, NULL,
|
|
406
|
NULL, NULL, NULL, NULL),
|
|
407
|
_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
|
|
408
|
NULL, NULL, NULL, NULL,
|
|
409
|
NULL, NULL, NULL, NULL),
|
|
410
|
_AM33XX_MUXENTRY(EXT_WAKEUP, 0,
|
|
411
|
NULL, NULL, NULL, NULL,
|
|
412
|
NULL, NULL, NULL, NULL),
|
|
413
|
_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
|
|
414
|
"usb0_drvvbus", NULL, NULL, NULL,
|
|
415
|
NULL, NULL, NULL, NULL),
|
|
416
|
_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
|
|
417
|
"usb1_drvvbus", NULL, NULL, NULL,
|
|
418
|
NULL, NULL, NULL, "gpio3_13"),
|
|
419
|
_AM33XX_MUXENTRY(DDR_RESETN, 0,
|
|
420
|
NULL, NULL, NULL, NULL,
|
|
421
|
NULL, NULL, NULL, NULL),
|
|
422
|
_AM33XX_MUXENTRY(DDR_CSN0, 0,
|
|
423
|
NULL, NULL, NULL, NULL,
|
|
424
|
NULL, NULL, NULL, NULL),
|
|
425
|
_AM33XX_MUXENTRY(DDR_CKE, 0,
|
|
426
|
NULL, NULL, NULL, NULL,
|
|
427
|
NULL, NULL, NULL, NULL),
|
|
428
|
_AM33XX_MUXENTRY(DDR_CK, 0,
|
|
429
|
NULL, NULL, NULL, NULL,
|
|
430
|
NULL, NULL, NULL, NULL),
|
|
431
|
_AM33XX_MUXENTRY(DDR_CKN, 0,
|
|
432
|
NULL, NULL, NULL, NULL,
|
|
433
|
NULL, NULL, NULL, NULL),
|
|
434
|
_AM33XX_MUXENTRY(DDR_CASN, 0,
|
|
435
|
NULL, NULL, NULL, NULL,
|
|
436
|
NULL, NULL, NULL, NULL),
|
|
437
|
_AM33XX_MUXENTRY(DDR_RASN, 0,
|
|
438
|
NULL, NULL, NULL, NULL,
|
|
439
|
NULL, NULL, NULL, NULL),
|
|
440
|
_AM33XX_MUXENTRY(DDR_WEN, 0,
|
|
441
|
NULL, NULL, NULL, NULL,
|
|
442
|
NULL, NULL, NULL, NULL),
|
|
443
|
_AM33XX_MUXENTRY(DDR_BA0, 0,
|
|
444
|
NULL, NULL, NULL, NULL,
|
|
445
|
NULL, NULL, NULL, NULL),
|
|
446
|
_AM33XX_MUXENTRY(DDR_BA1, 0,
|
|
447
|
NULL, NULL, NULL, NULL,
|
|
448
|
NULL, NULL, NULL, NULL),
|
|
449
|
_AM33XX_MUXENTRY(DDR_BA2, 0,
|
|
450
|
NULL, NULL, NULL, NULL,
|
|
451
|
NULL, NULL, NULL, NULL),
|
|
452
|
_AM33XX_MUXENTRY(DDR_A0, 0,
|
|
453
|
NULL, NULL, NULL, NULL,
|
|
454
|
NULL, NULL, NULL, NULL),
|
|
455
|
_AM33XX_MUXENTRY(DDR_A1, 0,
|
|
456
|
NULL, NULL, NULL, NULL,
|
|
457
|
NULL, NULL, NULL, NULL),
|
|
458
|
_AM33XX_MUXENTRY(DDR_A2, 0,
|
|
459
|
NULL, NULL, NULL, NULL,
|
|
460
|
NULL, NULL, NULL, NULL),
|
|
461
|
_AM33XX_MUXENTRY(DDR_A3, 0,
|
|
462
|
NULL, NULL, NULL, NULL,
|
|
463
|
NULL, NULL, NULL, NULL),
|
|
464
|
_AM33XX_MUXENTRY(DDR_A4, 0,
|
|
465
|
NULL, NULL, NULL, NULL,
|
|
466
|
NULL, NULL, NULL, NULL),
|
|
467
|
_AM33XX_MUXENTRY(DDR_A5, 0,
|
|
468
|
NULL, NULL, NULL, NULL,
|
|
469
|
NULL, NULL, NULL, NULL),
|
|
470
|
_AM33XX_MUXENTRY(DDR_A6, 0,
|
|
471
|
NULL, NULL, NULL, NULL,
|
|
472
|
NULL, NULL, NULL, NULL),
|
|
473
|
_AM33XX_MUXENTRY(DDR_A7, 0,
|
|
474
|
NULL, NULL, NULL, NULL,
|
|
475
|
NULL, NULL, NULL, NULL),
|
|
476
|
_AM33XX_MUXENTRY(DDR_A8, 0,
|
|
477
|
NULL, NULL, NULL, NULL,
|
|
478
|
NULL, NULL, NULL, NULL),
|
|
479
|
_AM33XX_MUXENTRY(DDR_A9, 0,
|
|
480
|
NULL, NULL, NULL, NULL,
|
|
481
|
NULL, NULL, NULL, NULL),
|
|
482
|
_AM33XX_MUXENTRY(DDR_A10, 0,
|
|
483
|
NULL, NULL, NULL, NULL,
|
|
484
|
NULL, NULL, NULL, NULL),
|
|
485
|
_AM33XX_MUXENTRY(DDR_A11, 0,
|
|
486
|
NULL, NULL, NULL, NULL,
|
|
487
|
NULL, NULL, NULL, NULL),
|
|
488
|
_AM33XX_MUXENTRY(DDR_A12, 0,
|
|
489
|
NULL, NULL, NULL, NULL,
|
|
490
|
NULL, NULL, NULL, NULL),
|
|
491
|
_AM33XX_MUXENTRY(DDR_A13, 0,
|
|
492
|
NULL, NULL, NULL, NULL,
|
|
493
|
NULL, NULL, NULL, NULL),
|
|
494
|
_AM33XX_MUXENTRY(DDR_A14, 0,
|
|
495
|
NULL, NULL, NULL, NULL,
|
|
496
|
NULL, NULL, NULL, NULL),
|
|
497
|
_AM33XX_MUXENTRY(DDR_A15, 0,
|
|
498
|
NULL, NULL, NULL, NULL,
|
|
499
|
NULL, NULL, NULL, NULL),
|
|
500
|
_AM33XX_MUXENTRY(DDR_ODT, 0,
|
|
501
|
NULL, NULL, NULL, NULL,
|
|
502
|
NULL, NULL, NULL, NULL),
|
|
503
|
_AM33XX_MUXENTRY(DDR_D0, 0,
|
|
504
|
NULL, NULL, NULL, NULL,
|
|
505
|
NULL, NULL, NULL, NULL),
|
|
506
|
_AM33XX_MUXENTRY(DDR_D1, 0,
|
|
507
|
NULL, NULL, NULL, NULL,
|
|
508
|
NULL, NULL, NULL, NULL),
|
|
509
|
_AM33XX_MUXENTRY(DDR_D2, 0,
|
|
510
|
NULL, NULL, NULL, NULL,
|
|
511
|
NULL, NULL, NULL, NULL),
|
|
512
|
_AM33XX_MUXENTRY(DDR_D3, 0,
|
|
513
|
NULL, NULL, NULL, NULL,
|
|
514
|
NULL, NULL, NULL, NULL),
|
|
515
|
_AM33XX_MUXENTRY(DDR_D4, 0,
|
|
516
|
NULL, NULL, NULL, NULL,
|
|
517
|
NULL, NULL, NULL, NULL),
|
|
518
|
_AM33XX_MUXENTRY(DDR_D5, 0,
|
|
519
|
NULL, NULL, NULL, NULL,
|
|
520
|
NULL, NULL, NULL, NULL),
|
|
521
|
_AM33XX_MUXENTRY(DDR_D6, 0,
|
|
522
|
NULL, NULL, NULL, NULL,
|
|
523
|
NULL, NULL, NULL, NULL),
|
|
524
|
_AM33XX_MUXENTRY(DDR_D7, 0,
|
|
525
|
NULL, NULL, NULL, NULL,
|
|
526
|
NULL, NULL, NULL, NULL),
|
|
527
|
_AM33XX_MUXENTRY(DDR_D8, 0,
|
|
528
|
NULL, NULL, NULL, NULL,
|
|
529
|
NULL, NULL, NULL, NULL),
|
|
530
|
_AM33XX_MUXENTRY(DDR_D9, 0,
|
|
531
|
NULL, NULL, NULL, NULL,
|
|
532
|
NULL, NULL, NULL, NULL),
|
|
533
|
_AM33XX_MUXENTRY(DDR_D10, 0,
|
|
534
|
NULL, NULL, NULL, NULL,
|
|
535
|
NULL, NULL, NULL, NULL),
|
|
536
|
_AM33XX_MUXENTRY(DDR_D11, 0,
|
|
537
|
NULL, NULL, NULL, NULL,
|
|
538
|
NULL, NULL, NULL, NULL),
|
|
539
|
_AM33XX_MUXENTRY(DDR_D12, 0,
|
|
540
|
NULL, NULL, NULL, NULL,
|
|
541
|
NULL, NULL, NULL, NULL),
|
|
542
|
_AM33XX_MUXENTRY(DDR_D13, 0,
|
|
543
|
NULL, NULL, NULL, NULL,
|
|
544
|
NULL, NULL, NULL, NULL),
|
|
545
|
_AM33XX_MUXENTRY(DDR_D14, 0,
|
|
546
|
NULL, NULL, NULL, NULL,
|
|
547
|
NULL, NULL, NULL, NULL),
|
|
548
|
_AM33XX_MUXENTRY(DDR_D15, 0,
|
|
549
|
NULL, NULL, NULL, NULL,
|
|
550
|
NULL, NULL, NULL, NULL),
|
|
551
|
_AM33XX_MUXENTRY(DDR_DQM0, 0,
|
|
552
|
NULL, NULL, NULL, NULL,
|
|
553
|
NULL, NULL, NULL, NULL),
|
|
554
|
_AM33XX_MUXENTRY(DDR_DQM1, 0,
|
|
555
|
NULL, NULL, NULL, NULL,
|
|
556
|
NULL, NULL, NULL, NULL),
|
|
557
|
_AM33XX_MUXENTRY(DDR_DQS0, 0,
|
|
558
|
NULL, NULL, NULL, NULL,
|
|
559
|
NULL, NULL, NULL, NULL),
|
|
560
|
_AM33XX_MUXENTRY(DDR_DQSN0, 0,
|
|
561
|
NULL, NULL, NULL, NULL,
|
|
562
|
NULL, NULL, NULL, NULL),
|
|
563
|
_AM33XX_MUXENTRY(DDR_DQS1, 0,
|
|
564
|
NULL, NULL, NULL, NULL,
|
|
565
|
NULL, NULL, NULL, NULL),
|
|
566
|
_AM33XX_MUXENTRY(DDR_DQSN1, 0,
|
|
567
|
NULL, NULL, NULL, NULL,
|
|
568
|
NULL, NULL, NULL, NULL),
|
|
569
|
_AM33XX_MUXENTRY(DDR_VREF, 0,
|
|
570
|
NULL, NULL, NULL, NULL,
|
|
571
|
NULL, NULL, NULL, NULL),
|
|
572
|
_AM33XX_MUXENTRY(DDR_VTP, 0,
|
|
573
|
NULL, NULL, NULL, NULL,
|
|
574
|
NULL, NULL, NULL, NULL),
|
|
575
|
_AM33XX_MUXENTRY(AIN0, 0,
|
|
576
|
"ain0", NULL, NULL, NULL,
|
|
577
|
NULL, NULL, NULL, NULL),
|
|
578
|
_AM33XX_MUXENTRY(AIN1, 0,
|
|
579
|
"ain1", NULL, NULL, NULL,
|
|
580
|
NULL, NULL, NULL, NULL),
|
|
581
|
_AM33XX_MUXENTRY(AIN2, 0,
|
|
582
|
"ain2", NULL, NULL, NULL,
|
|
583
|
NULL, NULL, NULL, NULL),
|
|
584
|
_AM33XX_MUXENTRY(AIN3, 0,
|
|
585
|
"ain3", NULL, NULL, NULL,
|
|
586
|
NULL, NULL, NULL, NULL),
|
|
587
|
_AM33XX_MUXENTRY(VREFP, 0,
|
|
588
|
"vrefp", NULL, NULL, NULL,
|
|
589
|
NULL, NULL, NULL, NULL),
|
|
590
|
_AM33XX_MUXENTRY(VREFN, 0,
|
|
591
|
"vrefn", NULL, NULL, NULL,
|
|
592
|
NULL, NULL, NULL, NULL),
|
|
593
|
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
|
594
|
};
|
|
595
|
|
|
596
|
int __init am33xx_mux_init(struct omap_board_mux *board_subset)
|
|
597
|
{
|
|
598
|
return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
|
|
599
|
AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
|
|
600
|
NULL, board_subset, NULL);
|
|
601
|
}
|
|
602
|
#else
|
|
603
|
int __init am33xx_mux_init(struct omap_board_mux *board_subset)
|
|
604
|
{
|
|
605
|
return 0;
|
|
606
|
}
|
|
607
|
#endif
|
