| 176 |
176 |
>;
|
| 177 |
177 |
};
|
| 178 |
178 |
|
| 179 |
|
/* nandflash_pins_default: nandflash_pins_default { */
|
| 180 |
|
/* pinctrl-single,pins = < */
|
| 181 |
|
/* 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad0.gpmc_ad0 *\/ */
|
| 182 |
|
/* 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad1.gpmc_ad1 *\/ */
|
| 183 |
|
/* 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad2.gpmc_ad2 *\/ */
|
| 184 |
|
/* 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad3.gpmc_ad3 *\/ */
|
| 185 |
|
/* 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad4.gpmc_ad4 *\/ */
|
| 186 |
|
/* 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad5.gpmc_ad5 *\/ */
|
| 187 |
|
/* 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad6.gpmc_ad6 *\/ */
|
| 188 |
|
/* 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad7.gpmc_ad7 *\/ */
|
| 189 |
|
/* 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_wait0.gpmc_wait0 *\/ */
|
| 190 |
|
/* 0x074 (PIN_INPUT_PULLUP | MUX_MODE7) /\* gpmc_wpn.gpio0_30 *\/ */
|
| 191 |
|
/* 0x07c (PIN_OUTPUT | MUX_MODE0) /\* gpmc_csn0.gpmc_csn0 *\/ */
|
| 192 |
|
/* 0x090 (PIN_OUTPUT | MUX_MODE0) /\* gpmc_advn_ale.gpmc_advn_ale *\/ */
|
| 193 |
|
/* 0x094 (PIN_OUTPUT | MUX_MODE0) /\* gpmc_oen_ren.gpmc_oen_ren *\/ */
|
| 194 |
|
/* 0x098 (PIN_OUTPUT | MUX_MODE0) /\* gpmc_wen.gpmc_wen *\/ */
|
| 195 |
|
/* 0x09c (PIN_OUTPUT | MUX_MODE0) /\* gpmc_be0n_cle.gpmc_be0n_cle *\/ */
|
| 196 |
|
/* >; */
|
| 197 |
|
/* }; */
|
|
179 |
/* RAD - Updated for MitySOM-335x */
|
|
180 |
nandflash_pins_default: nandflash_pins_default {
|
|
181 |
pinctrl-single,pins = <
|
|
182 |
0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
|
183 |
0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
|
184 |
0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
|
185 |
0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
|
186 |
0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
|
187 |
0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
|
188 |
0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
|
189 |
0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
|
190 |
0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
|
191 |
0x074 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wpn.gpmc_wpn */
|
|
192 |
0x07c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
|
193 |
0x090 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
|
194 |
0x094 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
|
195 |
0x098 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
|
196 |
0x09c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0_cle.gpmc_be0_cle */
|
|
197 |
>;
|
|
198 |
};
|
| 198 |
199 |
|
| 199 |
|
/* nandflash_pins_sleep: nandflash_pins_sleep { */
|
| 200 |
|
/* pinctrl-single,pins = < */
|
| 201 |
|
/* 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 202 |
|
/* 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 203 |
|
/* 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 204 |
|
/* 0xc (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 205 |
|
/* 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 206 |
|
/* 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 207 |
|
/* 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 208 |
|
/* 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 209 |
|
/* 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 210 |
|
/* 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 211 |
|
/* 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 212 |
|
/* 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 213 |
|
/* 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 214 |
|
/* 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 215 |
|
/* 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
|
| 216 |
|
/* >; */
|
| 217 |
|
/* }; */
|
|
200 |
/* RAD - Updated for MitySOM-335x */
|
|
201 |
nandflash_pins_sleep: nandflash_pins_sleep {
|
|
202 |
pinctrl-single,pins = <
|
|
203 |
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
204 |
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
205 |
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
206 |
0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
207 |
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
208 |
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
209 |
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
210 |
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
211 |
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
212 |
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
213 |
0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
214 |
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
215 |
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
216 |
0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
217 |
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
218 |
>;
|
|
219 |
};
|
| 218 |
220 |
|
| 219 |
221 |
/* ecap0_pins_default: backlight_pins { */
|
| 220 |
222 |
/* pinctrl-single,pins = < */
|
| ... | ... | |
| 516 |
518 |
*/
|
| 517 |
519 |
|
| 518 |
520 |
|
| 519 |
|
/* &gpmc { */
|
| 520 |
|
/* status = "okay"; */
|
| 521 |
|
/* pinctrl-names = "default", "sleep"; */
|
| 522 |
|
/* pinctrl-0 = <&nandflash_pins_default>; */
|
| 523 |
|
/* pinctrl-1 = <&nandflash_pins_sleep>; */
|
| 524 |
|
/* ranges = <0 0 0x08000000 0x10000000>; /\* CS0: NAND *\/ */
|
| 525 |
|
/* nand@0,0 { */
|
| 526 |
|
/* reg = <0 0 0>; /\* CS0, offset 0 *\/ */
|
| 527 |
|
/* ti,nand-ecc-opt = "bch8"; */
|
| 528 |
|
/* ti,elm-id = <&elm>; */
|
| 529 |
|
/* nand-bus-width = <8>; */
|
| 530 |
|
/* gpmc,device-width = <1>; */
|
| 531 |
|
/* gpmc,sync-clk-ps = <0>; */
|
| 532 |
|
/* gpmc,cs-on-ns = <0>; */
|
| 533 |
|
/* gpmc,cs-rd-off-ns = <44>; */
|
| 534 |
|
/* gpmc,cs-wr-off-ns = <44>; */
|
| 535 |
|
/* gpmc,adv-on-ns = <6>; */
|
| 536 |
|
/* gpmc,adv-rd-off-ns = <34>; */
|
| 537 |
|
/* gpmc,adv-wr-off-ns = <44>; */
|
| 538 |
|
/* gpmc,we-on-ns = <0>; */
|
| 539 |
|
/* gpmc,we-off-ns = <40>; */
|
| 540 |
|
/* gpmc,oe-on-ns = <0>; */
|
| 541 |
|
/* gpmc,oe-off-ns = <54>; */
|
| 542 |
|
/* gpmc,access-ns = <64>; */
|
| 543 |
|
/* gpmc,rd-cycle-ns = <82>; */
|
| 544 |
|
/* gpmc,wr-cycle-ns = <82>; */
|
| 545 |
|
/* gpmc,wait-on-read = "true"; */
|
| 546 |
|
/* gpmc,wait-on-write = "true"; */
|
| 547 |
|
/* gpmc,bus-turnaround-ns = <0>; */
|
| 548 |
|
/* gpmc,cycle2cycle-delay-ns = <0>; */
|
| 549 |
|
/* gpmc,clk-activation-ns = <0>; */
|
| 550 |
|
/* gpmc,wait-monitoring-ns = <0>; */
|
| 551 |
|
/* gpmc,wr-access-ns = <40>; */
|
| 552 |
|
/* gpmc,wr-data-mux-bus-ns = <0>; */
|
| 553 |
|
/* /\* MTD partition table *\/ */
|
| 554 |
|
/* /\* All SPL-* partitions are sized to minimal length */
|
| 555 |
|
/* * which can be independently programmable. For */
|
| 556 |
|
/* * NAND flash this is equal to size of erase-block *\/ */
|
| 557 |
|
/* #address-cells = <1>; */
|
| 558 |
|
/* #size-cells = <1>; */
|
| 559 |
|
/* partition@0 { */
|
| 560 |
|
/* label = "NAND.SPL"; */
|
| 561 |
|
/* reg = <0x00000000 0x000020000>; */
|
| 562 |
|
/* }; */
|
| 563 |
|
/* partition@1 { */
|
| 564 |
|
/* label = "NAND.SPL.backup1"; */
|
| 565 |
|
/* reg = <0x00020000 0x00020000>; */
|
| 566 |
|
/* }; */
|
| 567 |
|
/* partition@2 { */
|
| 568 |
|
/* label = "NAND.SPL.backup2"; */
|
| 569 |
|
/* reg = <0x00040000 0x00020000>; */
|
| 570 |
|
/* }; */
|
| 571 |
|
/* partition@3 { */
|
| 572 |
|
/* label = "NAND.SPL.backup3"; */
|
| 573 |
|
/* reg = <0x00060000 0x00020000>; */
|
| 574 |
|
/* }; */
|
| 575 |
|
/* partition@4 { */
|
| 576 |
|
/* label = "NAND.u-boot-spl-os"; */
|
| 577 |
|
/* reg = <0x00080000 0x00040000>; */
|
| 578 |
|
/* }; */
|
| 579 |
|
/* partition@5 { */
|
| 580 |
|
/* label = "NAND.u-boot"; */
|
| 581 |
|
/* reg = <0x000C0000 0x00100000>; */
|
| 582 |
|
/* }; */
|
| 583 |
|
/* partition@6 { */
|
| 584 |
|
/* label = "NAND.u-boot-env"; */
|
| 585 |
|
/* reg = <0x001C0000 0x00020000>; */
|
| 586 |
|
/* }; */
|
| 587 |
|
/* partition@7 { */
|
| 588 |
|
/* label = "NAND.u-boot-env.backup1"; */
|
| 589 |
|
/* reg = <0x001E0000 0x00020000>; */
|
| 590 |
|
/* }; */
|
| 591 |
|
/* partition@8 { */
|
| 592 |
|
/* label = "NAND.kernel"; */
|
| 593 |
|
/* reg = <0x00200000 0x00800000>; */
|
| 594 |
|
/* }; */
|
| 595 |
|
/* partition@9 { */
|
| 596 |
|
/* label = "NAND.file-system"; */
|
| 597 |
|
/* reg = <0x00A00000 0x0F600000>; */
|
| 598 |
|
/* }; */
|
| 599 |
|
/* }; */
|
| 600 |
|
/* }; */
|
|
521 |
&gpmc {
|
|
522 |
status = "okay";
|
|
523 |
pinctrl-names = "default", "sleep";
|
|
524 |
pinctrl-0 = <&nandflash_pins_default>;
|
|
525 |
pinctrl-1 = <&nandflash_pins_sleep>;
|
|
526 |
ranges = <0 0 0x08000000 0x10000000>; /* CS0: 256 MB NAND */
|
|
527 |
nand@0,0 {
|
|
528 |
reg = <0 0 0>; /* CS0, offset 0 */
|
|
529 |
ti,nand-ecc-opt = "bch8"; /* from baseboard file */
|
|
530 |
ti,elm-id = <&elm>;
|
|
531 |
nand-bus-width = <8>;
|
|
532 |
gpmc,device-width = <1>;
|
|
533 |
gpmc,sync-clk-ps = <0>;
|
|
534 |
gpmc,cs-on-ns = <0>; /* from baseboard file */
|
|
535 |
gpmc,cs-rd-off-ns = <44>; /* from baseboard file */
|
|
536 |
gpmc,cs-wr-off-ns = <44>; /* from baseboard file */
|
|
537 |
gpmc,adv-on-ns = <6>; /* from baseboard file */
|
|
538 |
gpmc,adv-rd-off-ns = <34>; /* from baseboard file */
|
|
539 |
gpmc,adv-wr-off-ns = <44>; /* from baseboard file */
|
|
540 |
gpmc,we-on-ns = <0>;
|
|
541 |
gpmc,we-off-ns = <40>; /* from baseboard file */
|
|
542 |
gpmc,oe-on-ns = <0>;
|
|
543 |
gpmc,oe-off-ns = <54>; /* from baseboard file */
|
|
544 |
gpmc,access-ns = <64>; /* from baseboard file */
|
|
545 |
gpmc,rd-cycle-ns = <82>; /* from baseboard file */
|
|
546 |
gpmc,wr-cycle-ns = <82>; /* from baseboard file */
|
|
547 |
gpmc,wait-on-read = "true";
|
|
548 |
gpmc,wait-on-write = "true";
|
|
549 |
gpmc,bus-turnaround-ns = <0>;
|
|
550 |
gpmc,cycle2cycle-delay-ns = <0>;
|
|
551 |
gpmc,clk-activation-ns = <0>;
|
|
552 |
gpmc,wait-monitoring-ns = <0>;
|
|
553 |
gpmc,wr-access-ns = <40>; /* from baseboard file */
|
|
554 |
gpmc,wr-data-mux-bus-ns = <0>;
|
|
555 |
/* MTD partition table */
|
|
556 |
/* All SPL-* partitions are sized to minimal length
|
|
557 |
* which can be independently programmable. For
|
|
558 |
* NAND flash this is equal to size of erase-block */
|
|
559 |
#address-cells = <1>;
|
|
560 |
#size-cells = <1>;
|
|
561 |
partition@0 {
|
|
562 |
label = "NAND.SPL";
|
|
563 |
reg = <0x00000000 0x000020000>;
|
|
564 |
};
|
|
565 |
partition@1 {
|
|
566 |
label = "NAND.SPL.backup1";
|
|
567 |
reg = <0x00020000 0x00020000>;
|
|
568 |
};
|
|
569 |
partition@2 {
|
|
570 |
label = "NAND.SPL.backup2";
|
|
571 |
reg = <0x00040000 0x00020000>;
|
|
572 |
};
|
|
573 |
partition@3 {
|
|
574 |
label = "NAND.SPL.backup3";
|
|
575 |
reg = <0x00060000 0x00020000>;
|
|
576 |
};
|
|
577 |
partition@4 {
|
|
578 |
label = "NAND.u-boot";
|
|
579 |
reg = <0x00080000 0x001E0000>;
|
|
580 |
};
|
|
581 |
partition@5 {
|
|
582 |
label = "NAND.u-boot-env";
|
|
583 |
reg = <0x00260000 0x00020000>;
|
|
584 |
};
|
|
585 |
partition@6 {
|
|
586 |
label = "NAND.kernel";
|
|
587 |
reg = <0x00280000 0x00500000>;
|
|
588 |
};
|
|
589 |
partition@7 {
|
|
590 |
label = "NAND.file-system";
|
|
591 |
reg = <0x00780000 0x0F880000>;
|
|
592 |
};
|
|
593 |
};
|
|
594 |
};
|
| 601 |
595 |
|
| 602 |
596 |
|
| 603 |
597 |
|
