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MityDSP-L138 Starterware Example Code
Added by Bill Lichtinger over 12 years ago
The attached file contains TI's OMAP-L138 / AM1808 StarterWare package with additional examples for the MityDSP-L138 and MityARM-1808 SOMs. To work with the examples, open CCS 5 and choose [BASE_DIR]\ OMAPL138_StarterWare_1_10_03_03\build\armv5\cgt_ccs\omapl138\MityDSPL138 as the workspace, where [BASE_DIR] is the directory where the OMAPL138_StarterWare_1_10_03_03 folder resides.
The following examples have been implemented for the MityDSP-L138:
- cache_mmu
- dsp_exception
- edma
- gpio
- i2c
- ipc_buffer_io
- ipc_interrupt
- ipc_polling
- nand
- rtc
- spi
- spi_edma
- timer
- uart
- uart_edma
- wdt
Replies (2)
RE: MityDSP-L138 Starterware Example Code - Added by Shubham Khot almost 4 years ago
Hello
I am working on the LCDKOMAP-l138 board for the timer driver.
When using the Sysdelay function after having used the SysDelayTimerSetup the application hangs.
Studying the source code(platform/beaglebone/sysdelay.c)) the Sysdelay function uses the Timer 0.
Debugging the code I show that the Counter Register (TCRR) of the Timer receives the proper value show
that after x milisecs it will overflow. But when the TimerEnable(SOC_TMR_0_REGS, TMR_TIMER12, TMR_ENABLE_ONCE);
is invoked instead of setting the TCLR _ST bit of the TCLR register, the value of the TCRR is cleared and the value of TCLR remains zero.
This results in never starting the timer and the Sysdelay function to get stuck at the
while(flagIsrCnt);
As the Timer never started and now overflow occurs to trigger an interrupt.
Since the TCR receives the proper value, I assume that the timer is configured properly.
Then what is the problem?
RE: MityDSP-L138 Starterware Example Code - Added by Thomas Catalino almost 4 years ago
Hello -
You may wish to post this on one of the TI forums.
We are unable to support TI development kits.
If you are using one of our OMAPL138 based SOM modules in a product we may be able to help.
Thank you
