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CLK frequency increase using DSP only
Added by Arthur Helwig over 11 years ago
Hi,
I'm using a MityDSP-L138F board (L138-FI-225-RC). I'm porting an existing C6748-based DSP project, that gets in data through a high-speed interface (which I'm planning to use the FPGA and uPP interface for), and communicates with the outside world through the (console) UART interface. No need for any ARM-activity at all for now (we're planning on going that route at a later stage). One advantage of not having to boot Linux on the ARM at this stage seems to be that the boot time is nice and short.
Questions:
1) I'm planning to have u-Boot load the FPGA image, and then boot the DSP application using the bootdsp command. Any comments on this approach?
2) To ensure that the DSP has full control over all peripherals (including the console UART), I need to stop the ARM from the DSP. Using the CSL, the command: CSL_FINST(psc0Regs->MDCTL[CSL_PSC_ARM], PSC_MDCTL_LRST, ASSERT); seems to achieve the desired effect, placing the ARM in a permanent RESET state. Is this the recommended approach? More graceful approaches seem to rely on the ARM code itself being ready to receive a shutdown request, which I don't think is implemented in u-Boot at this time.
3) I'd like the DSP to run at 456 MHz. Do I need to increase the core voltage first? Is there example code that shows how to achieve this from the DSP? Could I potentially do it from the u-Boot commandline, using a series of mw.l commands?
4) Is it feasible to read and write a small amount (1 kB) of NAND/NOR flash memory from the DSP? This would allow for settings to be made permanent. Any example drivers for this?
Thanks,
Roger
Replies (6)
RE: CLK frequency increase using DSP only - Added by Michael Williamson over 11 years ago
Hello,
Some quick answers, though I must admit we don't normally abandon the ARM here in our applications, so you are on someone new ground....
1) I think this approach should work and would be the quickest / easiest to get you going. The only down side is that you'll need to ensure that your loaded DSP code avoids the ARM u-Boot area until after it has been loaded and launched.
2) There is no ARM shutdown request implemented at the moment. I think forcing it into reset is probably your best bet.
3) Yes, you will need to increase the voltage on the TPS65023 PMIC prior to boosting the PLL/OPP points. You should be able to do this using a uboot "script" (environment commands) with the i2c utilities. I will have to get back to you with the specific commands (I need to test them here first).
4) No reason why you can't have the DSP access the NAND or NOR once the ARM is put into reset. Just stay aware from the base of NOR (which has the first stage UBL and uBoot) or you'll brick your unit.
When I have the I2C commands for the PMIC voltage I'll follow up.
-Mike
RE: CLK frequency increase using DSP only - Added by Arthur Helwig over 11 years ago
Great - thanks Mike. In addition to increasing the voltage, I'd also be most grateful for a list of (DSP or u-Boot) commands that actually increase the frequency to 456 MHz, if you have them.
Thanks,
Roger
RE: CLK frequency increase using DSP only - Added by Michael Williamson over 11 years ago
OK.
The u-Boot / I2C commands to push the core voltage up to 1.3 volts, required for running at 456 MHz are as follows:
i2c mw 0x48 0x06.1 0x14 ## set DEFCORE to 1.3 volts
i2c mw 0x48 0x05.1 0xC0 ## enable transition to new voltage
The 456 MHz OPP must be achieved by setting the PLLM in the PLL0 directly to 456 MHz (multiply by 19). The other divisors are really application specific, so I'm not sure I can help you there. You should leave the PLL1 alone, as that has the base clock that governs the mDDR memory. You can only fool with that one while in the first stage user boot loader.
-Mike
RE: CLK frequency increase using DSP only - Added by Rex Taylor about 11 years ago
Hi, I too would like to increase the running speed towards 456MHz. I have managed to change the speed as per your instructions. and would like to have some further information.
Is there any documentation to explain the following
i2c mw 0x48 0x06.1 0x14 ## set DEFCORE to 1.3 volts
i2c mw 0x48 0x05.1 0xC0 ## enable transition to new voltage
How do I find out the frequency of OSCin for my MityDSP, type L138-FI-225-RC, and which OS frequencies can it support.
Many thanks,
Rex
RE: CLK frequency increase using DSP only - Added by Michael Williamson about 11 years ago
OSCin is 24 MHz. It's fixed by the crystal on the part.
The documentation you would need to read is for the TPS65023 PMIC from TI. These I2C commands modify the DCDC1 voltage controller to up the CORE voltage to 1.3 volts per the OMAP-L138 spec for the 456 MHZ OPP.
-Mike
RE: CLK frequency increase using DSP only - Added by Michael Williamson about 11 years ago
Check the Datasheet for the speed grade for the L138-FI-225-RC, though I think the F means CPU speed up to 456 MHz. The OMAP-L138 datasheet specifies all of the maximum operating frequencies for the clock domains within the part. The linux OS has management for the clock tree for several operating points. For StarterWare or other OS's not supported directly by CL, you'll need to contact the provider of the OS for additional support.
-Mike
