Forums » Software Development »
DSP connection to FPGA cores
Added by Steven Hill over 11 years ago
For previous history, see the various messages and replies in "Simple Example Needed" below. I was able to get a custom core running and operating correctly using memory mapping, connecting to the ARM half of the OMAP. But now I am faced with a more difficult problem. I am working on another core which will connect to the DSP half of the OMAP. This core is to be an interface to dual THS1206 12-bit ADCs. These devices have a "data available" output which I would like to use to generate an interrupt to the DSP which will trigger it to read data from them over the EMIF interface. I also plan to use the DSP to write configuration data to the THS1206 devices in response to another interrupt. I can't use memory mapping as this is only useful for the ARM processor. I see that the EMIFA core has provision for using CS4 and for generating interrupts to either the ARM or the DSP, but I don't know how to implement this functionality. Can anyone give me some assistance with this?
Replies (4)
RE: DSP connection to FPGA cores - Added by Michael Williamson over 11 years ago
I don't understand what you mean by "I can't use memory mapping as this is only useful for the ARM processor.".
The DSP (DSP/BIOS or SYS BIOS or bare metal code) can access the FPGA the same way as the ARM can. Just access the FPGA memory address just as you would a normal pointer. There is no memory management on the DSP.
What assistance do you need exactly? Help writing an interrupt handler? The core library in the MDK/BSP provides DSP/BIOS interrupt handling in the DspInterruptDispatch.cpp class. Any pin capable of acting as a GPIO can generate an interrupt condition on the processor. These interrupts can be routed to the ARM or the DSP (or both, but I don't advise that...).
-Mike
RE: DSP connection to FPGA cores - Added by Steven Hill over 11 years ago
Thanks for a very quick reply. So if I read or write from 0x66xxxxxx I will generate CS5 and if I read/write from 0x64xxxxxx I will generate CS4? Then if I route the interrupt output from my FPGA core to any of the GP0_0 through GP0_15 available GPIO pins I can the configure that pin to interrupt the DSP, correct? If I understand it correctly, the available interrupt generation through the base core module would not be the mechanism I would use to generate a DSP interrupt, because this relies on linux device drivers? Please correct me if I am wrong about any of these things...
RE: DSP connection to FPGA cores - Added by Steven Hill over 11 years ago
Should I assume that, since I have not had a reply to my last message, my comments in that message are correct?
