Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

hi,

I am having problems reading data from the FPGA to memory. I set up the UPP interface
using channel A from transmit, channel B for receive, and start the receive transactions
using the code below

#include "evmomapl137.h"
#define SHARED_BUFFER_RX 0x80010000

buffer = (uint8 *)SHARED_BUFFER_RX;

for(uint32 i = 0; i < len; i++)buffer[i] = 0; //initialize buffer

UPQD0 = SHARED_BUFFER_RX;
UPQD1 = 0x00010000 | len ; //one line of length "len"
UPQD2 = 0;

START_UPP_RX; //tell FPGA to write data to UPP

while(UPQS2 & 2); //wait until DMA done

//data is now in the shared buffer

This works fine when testing it inside a minimal test program.

However when I try to integrate it into an existing large and complex application,
I run into the following problem. It seems that the UPP DMA system can't access the
memory, not the shared buffer use above and not any other memory. After the DMA has
finished, the buffer still contains the initial values (0).

Is there any system setting, that can cause this kind of behaviour ?

The TX clk (upp_clk_a) is ok, therefore the clock for UPP the module is present.
I verified the UPP signals with an oscilloscope, they look ok.
I also tried to reinitialize the PINMUX registers and the UPP interface
before each transaction, but that doesn't help either.