Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi,

I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface

we have done following steps till date.

-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.
-- I have successfully run the example programs.
-- I have build new kernel with Analog Expansion support. We followed https://support.criticallink.com/redmine/projects/90-000173/wiki for the build of new kernel.
-- We have developed application in which DSP gets modulated data from ADC via FPGA interface. All the process is done in DSP and we are able to get demodulated output.
In this process FPGA reads data at 40MHz from ADC and sends data to uPP at 50 Mhz clock rate. everything is working fine.
-- Now we want to add extra features in DSP but we are not able to add as DSP doesn't have time to do all the task. So, we have transferred half of our job to FPGA side. Now
uPP will get data at 5 MHz clock rate. In this case, we are missing data from FPGA. I have implemented 3 buffers to get data from uPP with ping-pong buffer technique.My
each buffer size is 128*16. Will uPP work at 5 MHz frequency in receive mode? Becuse when we send data from FPGA with uPP clock rate of 12.5 MHz , we are missing less data
compare to 5 MHz clock rate. I have kept DMA receive thread priority 15, which is highest. What could be the reasons of missing data from FPGA to uPP? Please suggest.

Thanks,
Vivek Ponnani.