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NAND controller, EDMA3 and EMIFA priorities
Added by Mads Lind Christiansen over 13 years ago
Hi
I have a few questions regarding the NAND flash and EMIFA.
From the EDMA priority settings below (which I just dumped directly from the registers)
MSTPRI0 = 0x44442222
MSTPRI1 = 0x44440000
MSTPRI2 = 0x54604404
It seems EDMA3_0 TC0 and TC1 has the highest priority (over EDMA3_1).
I am using the EDMA3 LLD driver on queue 0.
I assume Queue 0 is EDMA3_0_TC0, queue 1 is EDMA3_0_TC1, queue 2 is EDMA3_1_TC0?
Is this correct?
What I need is to give EDMA3 higher priority on the EMIFA interface than NAND flash.
What I can see from the above EDMA3 priority settings, this seems already to be the case in OMAP L138 distro from Critical Link
What I am trying to figure out is how the NAND Flash Controller/Linux driver is using the EMIFA interface.
Is there anything else I can tweak to be sure that the NAND controller has lower priority than EMDA3 on the EMIFA?
We will sometimes in our system be dumping a file which contains a large amount of data (>MB) received from the DSP.
This will of course cause many writes to the NAND flash, so I would very much like to keep each NAND access as quick as possible.
Many thanks for any help,
Mads
Replies (1)
RE: NAND controller, EDMA3 and EMIFA priorities - Added by Michael Williamson over 13 years ago
Hi Mads,
I'm not sure there is much more you can do than what is already configured.
You might consider cross posting this over on TI's E2E site, as this is sort of a general OMAP-L138 question and there may be folks at TI who could shed more light on this issue.
The NAND/JFFS2/UBIFS (whatever you use) will likely be trying to write a 2K byte subpage + the OOB data (64 bytes) at a time. To my knowledge, it does not use a DMA but just CPU write cycles to memory (I will double check this tonight), so your DMA's will likely get in between byte/word write cycles to the NAND over the EMIFA when you need them.
Probably worth testing somehow (if you are comfortable with Xilinx Chipscope, you could probably watch the transfers and if you can preempty a NAND cycle).
-Mike
