Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

The UCF file in the board support package at MDK/fpga/vhdl/MityDSP_L138.ucf includes connection information between the UPP interface pins and the FPGA.

This is an excerpt:

#### Universal Parallel Port (uPP)
#NET "o_upp_2xtxclk" LOC = "F4" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_chb_clock" LOC = "T1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_chb_start" LOC = "T2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_chb_enable" LOC = "M3" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_chb_wait" LOC = "P3" | IOSTANDARD = LVCMOS18;
#NET "io_upp_cha_clock" LOC = "H7" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_cha_start" LOC = "C1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_cha_enable" LOC = "H5" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_cha_wait" LOC = "L5" | IOSTANDARD = LVCMOS18;

#NET "io_upp_xd<15>" LOC = "M1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<14>" LOC = "L2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<13>" LOC = "H2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<12>" LOC = "L1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<11>" LOC = "K2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<10>" LOC = "H1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<9>" LOC = "K1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<8>" LOC = "J1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<7>" LOC = "L4" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<6>" LOC = "H4" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<5>" LOC = "P1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<4>" LOC = "P2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<3>" LOC = "H3" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<2>" LOC = "N1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<1>" LOC = "N2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_xd<0>" LOC = "G3" | IOSTANDARD = LVCMOS18;
#NET "io_upp_d<15>" LOC = "F3" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<14>" LOC = "D3" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<13>" LOC = "M5" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<12>" LOC = "D2" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<11>" LOC = "E3" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<10>" LOC = "D1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<9>" LOC = "E4" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<8>" LOC = "F1" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<7>" LOC = "F5" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<6>" LOC = "F6" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<5>" LOC = "G6" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<4>" LOC = "L6" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<3>" LOC = "J6" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<2>" LOC = "H6" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<1>" LOC = "K5" | IOSTANDARD = LVCMOS18; 
#NET "io_upp_d<0>" LOC = "L7" | IOSTANDARD = LVCMOS18;

-Mike

Thanks Mike for reply.

The question will be, to what pins DSP connected pins FPGA? It needs to be known for purposes PINMUX.

Oleh

I don't think that the UPP pins are pinmuxed (there is only one option if the UPP is used). See the MDK/sw/dsp/core/tcDspUpp.cpp for pinmux setting.

-Mike