FPGA CLOCK LOCATION
Added by Jesus Alejandro Alvarez Trejo about 7 years ago
Hello good day I developing a new project in ISE WEBPACK using the PROFIBUS DEVELOPMENT KIT with the MitySOM-1810F Processor Card.
I am programming the FPGA and this is my entity:
PORT(
CLK50 : IN STD_LOGIC;
RX : IN STD_LOGIC;
TX : OUT STD_LOGIC;
RST : IN STD_LOGIC; -- BORRA DATO, RESET
SW : IN STD_LOGIC_VECTOR (0 TO 7);
LEDS_RX : OUT STD_LOGIC_VECTOR (7 downto 0):="11111111"
);end SMG_LE;I want to implement a UART communication using the expansion pins so as you can see I need a clock in my design, the question is: Is there a clock available for the FPGA? , I was looking for it in the data sheet but I did not find it,
Thanks for your time,
Regards,
Alex.
Replies (2)
RE: FPGA CLOCK LOCATION - Added by Alexander Block about 7 years ago
Alex,
Thank you for reaching out to us about this question.
On our MitySOM-L138F family modules we have the EMIF bus from the OMAP-L138 connected to the Xilinx Spartan 6 FPGA to allow for communications of cores between the processor and FPGA (as shown on this Architecture Wiki page https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture).
As such the 100MHz clock from the EMIF bus is available at the FPGA. In our example FPGA project that is included with the MityDSP-L138 MDK (https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package) we have the following signal:
i_ema_clk : in std_logic; -- 100 MHz EMIF clock
That signal is connected in our UCF file to ball T8 of the FPGA
NET "i_ema_clk" LOC = "T8" | IOSTANDARD = LVCMOS33 ;
Which is wired on the MitySOM-L138 PCB between the FPGA and OMAP-L138 processor.
You can find this example FPGA top level .vhdl file in the MDK under the following location
MDK_2014-01-13\examples\industrial_io\fpga\vhdl\IndustrialIO_top.vhd and corresponding UCF MDK_2014-01-13\examples\industrial_io\fpga\vhdl\IndustrialIO_rev_C.ucf
If you are working in the Windows OS for ISE you can download a copy of the MDK in .zip format for Windows from this link (https://www.dropbox.com/s/aczq8eevf74a1x5/MDK_2014-01-13.zip?dl=0)
Please note that we do provide a number of FPGA cores which include both ARM and DSP drivers for said cores, including a UART core. We would highly recommend that you start with our example as the basis for your project to properly utilize the EMIF interface between the L138 and FPGA and then add in the necessary cores to your design. This page (https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers) provides more information about our FPGA Cores and an example of implementing one.
Hopefully this answers your question but please let us know if we can help further.
Alex
RE: FPGA CLOCK LOCATION - Added by Jesus Alejandro Alvarez Trejo about 7 years ago
Hello, Good day
Thank you for the answer, I have been working only with the FPGA without using the EMIF interface between the L138 and FPGA.
I want to implement a code done in VHDL and my design contains a clock in its operation logic, so...
So mi question is: Could I use the "i_ema_clk : in std_logic; -- 100 MHz EMIF clock" in an independent design using VHDL code or I should follow the steps which includes this page to use the clock?: https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers
Mi second question is: Is it necessary the EMIF interface between the L138 and FPGA to use the 100 Mhz clock?
Thank you for your time
Regards,
Alex
