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MityDSP-L138F SPI Signal Access

Added by Tom Riddle over 4 years ago

Hi,

I'm trying to figure out how best to gain access to one of the two SPI ports on the L138. I have an Industrial I/O board with an L138F module and we want to interface it with some external eval board hardware that has SPI slave components. From the carrier board design guide and schematics SPI1 is dedicated to the MCP2515, SPI0 is multiplexed with the MII. Since Ethernet is a must have SPI0 is out. We will not be using CAN functionality, but the signals from the module pin-out look like they are directly routed to U900 with no intermediate testpoints our jumper access. Two approaches come to mind

  • remove U900 to gain access to the SPI1 signals on the pads and jumper as needed.
  • implement an SPI interface/controller in the FPGA, .

With the SPI/FPGA route can you recommend what would be the best L138 interface (that is wired to the FPGA) to get the data in/out. We already plan to use the uPP port to access an external ADC/DAC. GPIO bit banging is the worst case scenario.

If there is another approach to consider we're all ears. Thanks in advance, Tom


Replies (4)

RE: MityDSP-L138F SPI Signal Access - Added by Jonathan Cormier over 4 years ago

Tom Riddle wrote:

Hi,

I'm trying to figure out how best to gain access to one of the two SPI ports on the L138. I have an Industrial I/O board with an L138F module and we want to interface it with some external eval board hardware that has SPI slave components. From the carrier board design guide and schematics SPI1 is dedicated to the MCP2515, SPI0 is multiplexed with the MII. Since Ethernet is a must have SPI0 is out. We will not be using CAN functionality, but the signals from the module pin-out look like they are directly routed to U900 with no intermediate testpoints our jumper access. Two approaches come to mind

  • remove U900 to gain access to the SPI1 signals on the pads and jumper as needed.

Yes this should work.

Note that according to the industrial io schematic, the CAN_SOMI/MOSI/CLK pins (SPI1) also go to connector J700 as well as the unused SPI1_SCS0 which would be chip select 0 for SPI1. If you used CS0 then you wouldn't have to remove the CAN chip.

  • implement an SPI interface/controller in the FPGA, .
    With the SPI/FPGA route can you recommend what would be the best L138 interface (that is wired to the FPGA) to get the data in/out. We already plan to use the uPP port to access an external ADC/DAC. GPIO bit banging is the worst case scenario.

We do have a fpga spi core you could connect to whichever FPGA_IO pins you like. Most of them go to connectors J701/702.

You could also use the pins on connector J104 which is on top of the board as all the DISP_* and TS_* nets go to the fpga was well.

If there is another approach to consider we're all ears. Thanks in advance, Tom

RE: MityDSP-L138F SPI Signal Access - Added by Tom Riddle over 4 years ago

Thanks Jonathan... That's great, somehow overlooked those SPI1 signals on J700 since the connector assignment listed them as RESERVED.

First I'd like to make sure I haven't overlooked anything interface wise. We need these functions directly available from the Industrial I/O board, no need to utilize any of the others ie: CAN, Audio Out, RS-485, etc.

• EMAC (MII), (MDIO) - RJ45 connector
• MMC/SD0 – Micro-SD connector
• UART1 (no RTS, CTS) - J502 connector, adapter cable
• USB1 - USB-A connector
• uPP - FPGA

To interface our external HW we need I2C, SPI, McBSP and GPIO, and confirmed there is access to these L138 functions

• I2C0 - J701
• SPI1 - J700
• GPIO - J700

Now McBSP1 and I2C1 look available. Running the TI pinmux tool shows no conflicts with the ones above and access to the signals can be had as follows:

• I2C1 - J504 (only, not on an expansion header?)
• McBSP1 - J701

Have I overlooked anything? Also WRT to the FPGA SPI core, just curious, can the L138 communicate/interface with that core, if so is this over a mmap interface or something else?

Thanks, Tom

RE: MityDSP-L138F SPI Signal Access - Added by Tom Riddle over 4 years ago

Hi Jonathan,

Following up here... I was reading the link

https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/SPI_Access_Options

and had overlooked the fact that CS0 appears to be dedicated to the NOR flash. The schematics do show that signal on J700 pin 29. But the SPI1_SCS1 used for CAN_CS_N appears only to go to U900, I figure that is the CS I would use such that the NOR remains functional. Alternatives are to use a discrete GPIO as a CS or jumper from U900 to an FPGA pin on J702. Please confirm my understanding here. Thanks, Tom

RE: MityDSP-L138F SPI Signal Access - Added by Jonathan Cormier over 4 years ago

Yes, Good catch. Sorry about that.

Using a gpio pin for a chip select should work fine. Looks like there are 4 already on that connector. See this link for how we use the gpio as chip selects in the existing industrial io baseboard file. https://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=arch/arm/mach-davinci/baseboard-industrialio.c;h=112cbf0f19942494dd521adaf5e8bf411a6a7f3a;hb=refs/heads/mitydsp-linux-v3.2#l360

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