MightyDspL138 Factory Test and labeling
When tested at the factory, is a "bit scan" of some sort done to determine that all the connections between the FPGA and the L138 are intact? We are having a problem with a single SOM that has alluded our ability to figure out what the problem may be; for the most part, it works fine, but it produces "warped" data. We've traced it to the SOM rather than the carrier board, but have not been able to go further. Would running it back through the CL factory test be an option?
Also, do you have a document on how to interpret the s/n & batch code labels that are applied to the SOM's? We'd like to compare the bad SOM batch codes with others we may have to help us understand some risk.
Thanks, Fred Weiser
Thank you for reaching out to us about this question.
During production test the FPGA IO pins at the edge connector are tested as well as those between the OMAP and FPGA. Prior to having you return/RMA the module can you provide a copy of the UCF file that is used for your FPGA image? I'd like to review all the pins that are mapped between the processor and FPGA for your use case. If the UCF is sensitive in nature feel free to e-mail me at email@example.com.
Additionally is this module one that had been operating normally for some amount of time and then began experiencing "warped" data or was it a brand new unit that failed during initial testing?
The best identifier on our products is going to be the lot code which is noted as YY-MM-BB (YY = Year of build, MM = Month of build and BB = build # of the month) on the last line of the product label. For example all units with the 15-03-01 lot code would have been built at the same time.
Sorry for the inconvenience,