L138F - FPGA gets incorrect data from UPP
Added by Marek Bartu over 11 years ago
Hello,
I have problem when trying to read data on UPP by FPGA (sent from OMAP - working with L138F, XC6SLX45, ISE WebPack 14.3). Data arrive corrupted. The reason might be latence on CLK when routed to clock tree via logic blocks in FPGA - sometimes it is possible to avoid errors by setting proper phase shift, but every design update requires additional adjustment.
Is there any clock source that is synchronous to the data on UPP and is correctly attached to some GCLK port on FPGA side?
thanks, Marek
Replies (1)
RE: L138F - FPGA gets incorrect data from UPP - Added by Michael Williamson over 11 years ago
Marek,
The UPP clocks may be sourced by either the FPGA or the OMAP-L138 based on your configuration requirements. If sourced by the OMAP-L138, you should be able to run the input clock to a DCM or a PLL and align the data-eyes on the Tx or Rx data per the TI specification. The UPP_CH0_CLK and UPP_CH1_CLK connections are admittedly not made to the GCLK ports on the FPGA, but we have not had any problems finding a stable timing constraint / phase with the clock rates (75 MHz max single data rate) with reasonable timing constraints (OFFSET_IN, etc.) on the input pin. There is a local routing delay, but the tools should be able to determine what it is.
If you source the clock with the FPGA, you should be able to source the clock using a DDR2 element and (with a proper constraint) not have a random phase on the output clock with respect to the data lines.
-Mike
