Programming FPGA on power up issues
Added by minh tung over 10 years ago
Hi,
I am using MityDSP-L138F and Carrier Board.
I developed new FPGA system that included only Upp Interface, DCM (Input clock: 100MHz, output clock 75MHz) (I removed base_module, emif interface ,...) can be connect with OMAPL138.
First,I using JTAG to program FPGA, the system run fine and DONE LED was light up.
Second, when I try to create .bin file and loading via CPU. It cannot run and DONE LEN wasn't light up.
(I follow instruction:
(1)http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview
(2)http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA
)
But, When I using industrialio_top.bit (MDK_2011-12-05\examples\industrial_io\fpga\build_dvi_rev_a_b) to create industrialio_top.bin and loading via CPU (Do the same way as befor) and there is DONE LED.
Can you give me some instruction to find out the problems in my program?
I am looking forward for your replying.
Thank,
Replies (4)
RE: Programming FPGA on power up issues - Added by Michael Williamson over 10 years ago
How are you loading via CPU, linux or via u-Boot?
RE: Programming FPGA on power up issues - Added by minh tung over 10 years ago
I have done 2 way CPU,Linux and u-Boot. But result is the same.
RE: Programming FPGA on power up issues - Added by Michael Williamson over 10 years ago
Hi,
Sorry for the delay, are you still having issue here? Or have you solved the issue?
Can you dump your u-boot text when you try to program?
-Mike
RE: Programming FPGA on power up issues - Added by minh tung over 10 years ago
Hi,
We have resolved that issues.
We used EDK system to develop FPGA and we modified bitgen.ut below:
-g TdoPin:PULLNONE
#-g StartUpClk:JTAGCLK
-g DriveDone:YES
before that: we use -g StartUpClk:JTAGCLK and -g TdoPin:PULLNONE command only
I think the reasons is that: when use configure JTAGCLK to start up FPGA, CPU cannot boot up FPGA.
