Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

SB,

The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.

Please reference this Wiki page for information about programming the FPGA: https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA

Alex

I understand that. However, I would like to configure the FPGA in serial slave mode.

SB,

I apologize.

The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.

It may be possible to "remove" the M0 and M1 resistors which would allow the internal default pull-up signals to allow the Slave Serial mode to be used (Note 4 - Page 23: http://www.xilinx.com/support/documentation/user_guides/ug380.pdf). I will work with some of our engineering staff to see if there are any further considerations.

Alex

I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.

As well he wanted to know what the reasoning is behind programming the FPGA in the Slave Serial mode vs the current 8-bit parallel?

Thank you.

Thanks for the information.

We are prototyping a future product and due to pin count restrictions we can't use parallel slave mode.

How are the two resistors called, Rxxx and Ryyy ?

We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.

Thank you.

Alex