Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi,

I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
-- ADC5560 and DAC5672 is used.

we have done following steps till date.

-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.
-- I have successfully run the example programs.
-- I have build new kernel with Analog Expansion support. We followed https://support.criticallink.com/redmine/projects/90-000173/wiki for the build of new kernel.
-- We have developed application in which DSP gets modulated data from ADC via FPGA interface. All the process is done in DSP and we are able to get demodulated output.
In this process FPGA reads data at 40MHz from ADC and sends data to uPP at 50 Mhz clock rate. everything is working fine.
Now, we need to change the clocks in FPGA, as we need to do some processes in FPGA.
In FPGA program which is the reference program from AnalogExpansionSuite (from Critical Link), we have one doubt from the comment of UPP interface in IndustrialIO_top file.
We are using ADS5560 with 40MSPS.
There is a component declaration for ADS5560 as below
component ads5560
Port (
clk : in std_logic;
i_ABus : in std_logic_vector(5 downto 0);
i_DBus : in std_logic_vector(15 downto 0);
o_DBus : out std_logic_vector(15 downto 0);
i_wr_en : in std_logic;
i_rd_en : in std_logic;
i_cs : in std_logic;
o_irq : out std_logic := '0';
i_ilevel : in std_logic_vector(1 downto 0) := "00";
i_ivector : in std_logic_vector(3 downto 0) := "0000";

-- ADC interface
      i_adc_in_p      : in  std_logic_vector(7 downto 0);  -- DDR inputs
      i_adc_in_n      : in  std_logic_vector(7 downto 0);  -- DDR inputs
      i_adc_clk_p     : in  std_logic;
      i_adc_clk_n     : in  std_logic;
      i_adc_ovr       : in  std_logic;
     o_adc_clk       : out std_logic;

-- UPP interface
      i_upp_clock      : in  std_logic; -- from fabric, minimum 40 MHz
      o_upp_clock      : out std_logic;
      o_upp_d          : out std_logic_vector(15 downto 0);
      o_upp_enable     : out std_logic;
      o_upp_start      : out std_logic;
      i_upp_wait       : in  std_logic

);
end component;
The i_upp_clock signal is commented with the statement that from fabric, minimum 40 MHz
What does it mean? It means the clock we assign to i_upp_clock should always be more than 40 MHz? 
In example code from AnalogExpansionSuite , we understand that i_upp_clock is set to 50MHz which is from CLKDV of DCM_SP module. And this i_upp_clock is given to the uPP channel B of DSP. Channel B of uPP is set in receive mode in DSP. So, uPP of DSP gets clock of 50 MHz from FPGA.  So, finally in FPGA, It writes data in FIFO at 40 MHz and reads data from FIFO at 50 MHz.
As per comment 

i_upp_clock      : in  std_logic; -- from fabric, minimum 40 MHz

we can not assign i_upp_clock below 40 MHz. That means we can not give uPP clock below 40 MHz? Is it so? Please clarify.

Thanks,
Vivek Ponnani